173 lines
7.4 KiB
LLVM
173 lines
7.4 KiB
LLVM
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; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; GCN-LABEL: {{^}}extract_vector_elt_v2f16:
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; GCN: s_load_dword [[VEC:s[0-9]+]]
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; GCN: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], 16
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; GCN-DAG: v_mov_b32_e32 [[VELT0:v[0-9]+]], [[VEC]]
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; GCN-DAG: v_mov_b32_e32 [[VELT1:v[0-9]+]], [[ELT1]]
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; GCN-DAG: buffer_store_short [[VELT0]]
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; GCN-DAG: buffer_store_short [[VELT1]]
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define amdgpu_kernel void @extract_vector_elt_v2f16(half addrspace(1)* %out, <2 x half> addrspace(4)* %vec.ptr) #0 {
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%vec = load <2 x half>, <2 x half> addrspace(4)* %vec.ptr
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%p0 = extractelement <2 x half> %vec, i32 0
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%p1 = extractelement <2 x half> %vec, i32 1
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%out1 = getelementptr half, half addrspace(1)* %out, i32 10
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store half %p1, half addrspace(1)* %out, align 2
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store half %p0, half addrspace(1)* %out1, align 2
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ret void
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}
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; GCN-LABEL: {{^}}extract_vector_elt_v2f16_dynamic_sgpr:
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; GCN: s_load_dword [[IDX:s[0-9]+]]
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; GCN: s_load_dword [[VEC:s[0-9]+]]
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; GCN: s_lshl_b32 [[IDX_SCALED:s[0-9]+]], [[IDX]], 4
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; GCN: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], [[IDX_SCALED]]
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; GCN: v_mov_b32_e32 [[VELT1:v[0-9]+]], [[ELT1]]
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; GCN: buffer_store_short [[VELT1]]
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; GCN: ScratchSize: 0
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define amdgpu_kernel void @extract_vector_elt_v2f16_dynamic_sgpr(half addrspace(1)* %out, <2 x half> addrspace(4)* %vec.ptr, i32 %idx) #0 {
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%vec = load <2 x half>, <2 x half> addrspace(4)* %vec.ptr
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%elt = extractelement <2 x half> %vec, i32 %idx
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store half %elt, half addrspace(1)* %out, align 2
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ret void
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}
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; GCN-LABEL: {{^}}extract_vector_elt_v2f16_dynamic_vgpr:
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; GCN-DAG: s_load_dword [[VEC:s[0-9]+]]
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; GCN-DAG: {{flat|buffer}}_load_dword [[IDX:v[0-9]+]]
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; GCN: v_lshlrev_b32_e32 [[IDX_SCALED:v[0-9]+]], 4, [[IDX]]
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; SI: v_lshr_b32_e32 [[ELT:v[0-9]+]], [[VEC]], [[IDX_SCALED]]
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; VI: v_lshrrev_b32_e64 [[ELT:v[0-9]+]], [[IDX_SCALED]], [[VEC]]
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; SI: buffer_store_short [[ELT]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[ELT]]
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; GCN: ScratchSize: 0{{$}}
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define amdgpu_kernel void @extract_vector_elt_v2f16_dynamic_vgpr(half addrspace(1)* %out, <2 x half> addrspace(4)* %vec.ptr, i32 addrspace(1)* %idx.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %idx.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds half, half addrspace(1)* %out, i64 %tid.ext
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%vec = load <2 x half>, <2 x half> addrspace(4)* %vec.ptr
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%idx = load i32, i32 addrspace(1)* %gep
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%elt = extractelement <2 x half> %vec, i32 %idx
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store half %elt, half addrspace(1)* %out.gep, align 2
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ret void
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}
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; GCN-LABEL: {{^}}extract_vector_elt_v3f16:
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; GCN: s_load_dwordx2
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; GCN: s_load_dwordx2
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; GCN: buffer_store_short
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; GCN: buffer_store_short
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define amdgpu_kernel void @extract_vector_elt_v3f16(half addrspace(1)* %out, <3 x half> %foo) #0 {
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%p0 = extractelement <3 x half> %foo, i32 0
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%p1 = extractelement <3 x half> %foo, i32 2
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%out1 = getelementptr half, half addrspace(1)* %out, i32 1
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store half %p1, half addrspace(1)* %out, align 2
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store half %p0, half addrspace(1)* %out1, align 2
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ret void
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}
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; FIXME: Why sometimes vector shift?
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; GCN-LABEL: {{^}}dynamic_extract_vector_elt_v3f16:
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; SI: s_load_dword s
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; SI: s_load_dwordx2 s
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; SI: s_load_dwordx2 s
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; GFX89: s_load_dwordx2 s
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; GFX89: s_load_dwordx2 s
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; GFX89: s_load_dword s
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; GCN-DAG: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 4
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; GCN: s_lshr_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
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; GCN: {{buffer|global}}_store_short
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define amdgpu_kernel void @dynamic_extract_vector_elt_v3f16(half addrspace(1)* %out, <3 x half> %foo, i32 %idx) #0 {
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%p0 = extractelement <3 x half> %foo, i32 %idx
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%out1 = getelementptr half, half addrspace(1)* %out, i32 1
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store half %p0, half addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_extractelement_v4f16_2:
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; SI: buffer_load_dword [[LOAD:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; SI: buffer_store_short [[LOAD]]
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; VI: flat_load_dword v
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; VI: flat_store_short
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; GFX9: global_load_dword [[LOAD:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, off offset:4
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; GFX9: global_store_short_d16_hi v{{\[[0-9]+:[0-9]+\]}}, [[LOAD]]
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define amdgpu_kernel void @v_extractelement_v4f16_2(half addrspace(1)* %out, <4 x half> addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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%tid.ext = sext i32 %tid to i64
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%in.gep = getelementptr inbounds <4 x half>, <4 x half> addrspace(1)* %in, i64 %tid.ext
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%out.gep = getelementptr inbounds half, half addrspace(1)* %out, i64 %tid.ext
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%vec = load <4 x half>, <4 x half> addrspace(1)* %in.gep
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%vec.extract = extractelement <4 x half> %vec, i32 2
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store half %vec.extract, half addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}v_insertelement_v4f16_dynamic_vgpr:
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; GCN-DAG: {{flat|global|buffer}}_load_dword [[IDX:v[0-9]+]],
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; GCN-DAG: {{flat|global|buffer}}_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
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; GCN-DAG: v_lshlrev_b32_e32 [[SCALED_IDX:v[0-9]+]], 4, [[IDX]]
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; GFX89: v_lshrrev_b64 v{{\[}}[[SHIFT_LO:[0-9]+]]:[[SHIFT_HI:[0-9]+]]{{\]}}, [[SCALED_IDX]], v{{\[}}[[LO]]:[[HI]]{{\]}}
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; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[SHIFT_LO]]
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; SI: v_lshr_b64 v{{\[}}[[SHIFT_LO:[0-9]+]]:[[SHIFT_HI:[0-9]+]]{{\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}}, [[SCALED_IDX]]
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; SI: buffer_store_short v[[SHIFT_LO]]
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define amdgpu_kernel void @v_insertelement_v4f16_dynamic_vgpr(half addrspace(1)* %out, <4 x half> addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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%tid.ext = sext i32 %tid to i64
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%in.gep = getelementptr inbounds <4 x half>, <4 x half> addrspace(1)* %in, i64 %tid.ext
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%out.gep = getelementptr inbounds half, half addrspace(1)* %out, i64 %tid.ext
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%idx.val = load volatile i32, i32 addrspace(1)* undef
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%vec = load <4 x half>, <4 x half> addrspace(1)* %in.gep
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%vec.extract = extractelement <4 x half> %vec, i32 %idx.val
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store half %vec.extract, half addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}reduce_load_vector_v8f16_extract_01:
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; GCN: s_load_dwordx2 [[PTR:s\[[0-9]+:[0-9]+\]]],
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; GCN-NOT: {{s|buffer|flat|global}}_load_
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; GCN: s_load_dword s{{[0-9]+}}, [[PTR]], 0x0
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; GCN-NOT: {{s|buffer|flat|global}}_load_
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; GCN: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 16
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define amdgpu_kernel void @reduce_load_vector_v8f16_extract_01(<16 x half> addrspace(4)* %ptr) #0 {
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%load = load <16 x half>, <16 x half> addrspace(4)* %ptr
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%elt0 = extractelement <16 x half> %load, i32 0
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%elt1 = extractelement <16 x half> %load, i32 1
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store volatile half %elt0, half addrspace(1)* undef, align 2
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store volatile half %elt1, half addrspace(1)* undef, align 2
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ret void
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}
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; GCN-LABEL: {{^}}reduce_load_vector_v8f16_extract_23:
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; GCN: s_load_dwordx2 [[PTR:s\[[0-9]+:[0-9]+\]]],
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; GCN-NOT: {{s|buffer|flat|global}}_load_
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; GCN: s_load_dword s{{[0-9]+}}, [[PTR]], {{0x1|0x4}}
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; GCN-NOT: {{s|buffer|flat|global}}_load_
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; GCN: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 16
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define amdgpu_kernel void @reduce_load_vector_v8f16_extract_23(<16 x half> addrspace(4)* %ptr) #0 {
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%load = load <16 x half>, <16 x half> addrspace(4)* %ptr
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%elt2 = extractelement <16 x half> %load, i32 2
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%elt3 = extractelement <16 x half> %load, i32 3
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store volatile half %elt2, half addrspace(1)* undef, align 2
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store volatile half %elt3, half addrspace(1)* undef, align 2
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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