94 lines
3.1 KiB
LLVM
94 lines
3.1 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s
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; The generated code for this test uses a vld1.32 instruction
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; to write the lane 1 of a D register containing the value of
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; <2 x float> %B. Since the D register is defined, it would
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; be incorrect to fully write it (with a vmov.f64) before the
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; vld1.32 instruction. The test checks that a vmov.f64 was not
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; generated.
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define <2 x float> @t1(float* %A, <2 x float> %B) {
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; CHECK-LABEL: t1:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov d16, r2, r3
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; CHECK-NEXT: vld1.32 {d16[1]}, [r0:32]
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: bx lr
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%tmp2 = load float, float* %A, align 4
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%tmp3 = insertelement <2 x float> %B, float %tmp2, i32 1
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ret <2 x float> %tmp3
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}
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; The code generated by this test uses a vld1.32 instruction.
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; We check that a dependency breaking vmov* instruction was
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; generated.
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define void @t2(<4 x i8> *%in, <4 x i8> *%out, i32 %n) {
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; CHECK-LABEL: t2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: add r0, r0, #4
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; CHECK-NEXT: add r1, r1, #4
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; CHECK-NEXT: .LBB1_1: @ %loop
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vmov.f64 d16, #5.000000e-01
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; CHECK-NEXT: vld1.32 {d16[0]}, [r0:32]
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; CHECK-NEXT: vmovl.u8 q8, d16
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; CHECK-NEXT: vuzp.8 d16, d18
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; CHECK-NEXT: vst1.32 {d16[0]}, [r1:32]!
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; CHECK-NEXT: add r0, r0, #4
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; CHECK-NEXT: subs r2, r2, #1
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; CHECK-NEXT: beq .LBB1_1
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; CHECK-NEXT: @ %bb.2: @ %ret
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; CHECK-NEXT: bx lr
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entry:
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br label %loop
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loop:
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%oldcount = phi i32 [0, %entry], [%newcount, %loop]
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%newcount = add i32 %oldcount, 1
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%p1 = getelementptr <4 x i8>, <4 x i8> *%in, i32 %newcount
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%p2 = getelementptr <4 x i8>, <4 x i8> *%out, i32 %newcount
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%tmp1 = load <4 x i8> , <4 x i8> *%p1, align 4
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store <4 x i8> %tmp1, <4 x i8> *%p2
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%cmp = icmp eq i32 %newcount, %n
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br i1 %cmp, label %loop, label %ret
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ret:
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ret void
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}
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; If minimizing size, that overrides perf, so no extra vmov.f64 here.
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; TODO: This (and above) could use a splat load to remove the false
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; dependence with no extra instruction.
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define void @t2_minsize(<4 x i8> *%in, <4 x i8> *%out, i32 %n) minsize {
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; CHECK-LABEL: t2_minsize:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: add r0, r0, #4
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; CHECK-NEXT: add r1, r1, #4
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; CHECK-NEXT: .LBB2_1: @ %loop
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vld1.32 {d16[0]}, [r0:32]
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; CHECK-NEXT: vmovl.u8 q8, d16
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; CHECK-NEXT: vuzp.8 d16, d18
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; CHECK-NEXT: vst1.32 {d16[0]}, [r1:32]!
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; CHECK-NEXT: add r0, r0, #4
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; CHECK-NEXT: subs r2, r2, #1
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; CHECK-NEXT: beq .LBB2_1
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; CHECK-NEXT: @ %bb.2: @ %ret
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; CHECK-NEXT: bx lr
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entry:
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br label %loop
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loop:
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%oldcount = phi i32 [0, %entry], [%newcount, %loop]
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%newcount = add i32 %oldcount, 1
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%p1 = getelementptr <4 x i8>, <4 x i8> *%in, i32 %newcount
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%p2 = getelementptr <4 x i8>, <4 x i8> *%out, i32 %newcount
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%tmp1 = load <4 x i8> , <4 x i8> *%p1, align 4
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store <4 x i8> %tmp1, <4 x i8> *%p2
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%cmp = icmp eq i32 %newcount, %n
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br i1 %cmp, label %loop, label %ret
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ret:
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ret void
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}
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