74 lines
2.6 KiB
LLVM
74 lines
2.6 KiB
LLVM
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; RUN: llc -march=hexagon < %s
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; REQUIRES: asserts
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; The register coalescer created (via rematerialization) a definition of
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; a register (R0), which had "undef" flag set. This caused the def to be
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; ignored in the dependence graph, which then lead to an invalid instruction
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; move in the machine scheduler (and an assert).
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; The undef flags are already being cleared in the register cleanup, but
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; that happens after register allocation. The undef flags need to be cleared
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; earlier to avoid this issue.
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%0 = type <{ i8*, i8*, i16, i8, i8, i8 }>
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%1 = type { %2, %5, [3 x %3] }
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%2 = type { %3, %4, i16, i16 }
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%3 = type { i32, i32, i8, i8 }
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%4 = type { i32, i32, i32 }
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%5 = type { i8, i8, i8, i8, i32, i32, i16, i16, i32, i8, i8, i8, i32, i32, i16, i16, i32 }
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%6 = type { %7, i8, i16, i16, i8, i8, i8, i8, i8 }
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%7 = type { i32, i32, i16, i16, i16, i8 }
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@g0 = external constant %0, align 1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.M2.mpy.up(i32, i32) #1
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declare void @f0(%0*, i32, i32, i32, i32, i32)
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define void @f1(i8 zeroext %a0, %1* nocapture %a1, i8 zeroext %a2, i8 zeroext %a3) #0 {
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b0:
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%v0 = getelementptr inbounds %1, %1* %a1, i32 0, i32 1, i32 9
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%v1 = load i8, i8* %v0, align 1
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%v2 = zext i8 %v1 to i32
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%v3 = getelementptr inbounds %1, %1* %a1, i32 0, i32 2, i32 %v2
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%v4 = tail call %6* @f2(i32 undef, i8 zeroext 0)
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br i1 undef, label %b1, label %b5
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b1: ; preds = %b0
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%v5 = tail call i32 @llvm.hexagon.M2.mpy.up(i32 undef, i32 undef)
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%v6 = tail call i32 @llvm.hexagon.M2.mpy.up(i32 undef, i32 undef)
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%v7 = zext i32 %v5 to i64
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%v8 = zext i32 %v6 to i64
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%v9 = add nuw nsw i64 %v8, %v7
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%v10 = lshr i64 %v9, 5
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%v11 = trunc i64 %v10 to i32
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store i32 %v11, i32* undef, align 4
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br i1 undef, label %b3, label %b2
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b2: ; preds = %b1
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%v12 = getelementptr inbounds %3, %3* %v3, i32 0, i32 0
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store i32 0, i32* %v12, align 4
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tail call void @f0(%0* @g0, i32 undef, i32 0, i32 undef, i32 undef, i32 undef)
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br label %b4
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b3: ; preds = %b1
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br label %b4
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b4: ; preds = %b3, %b2
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unreachable
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b5: ; preds = %b0
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br i1 undef, label %b6, label %b7
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b6: ; preds = %b5
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unreachable
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b7: ; preds = %b5
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unreachable
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}
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declare %6* @f2(i32, i8 zeroext)
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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attributes #1 = { nounwind readnone }
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