66 lines
2.5 KiB
LLVM
66 lines
2.5 KiB
LLVM
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; RUN: llc -march=hexagon < %s | FileCheck %s
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;
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; Check that we do not generate v0 = vand(v1,v1)
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; CHECK-NOT: v{{[0-9]+}} = vand(v{{[0-9]+}},v{{[0-9]+}})
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; Function Attrs: nounwind
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define void @f0(i8* nocapture readonly %a0, i8* nocapture readonly %a1, i32 %a2, i8* nocapture %a3, i32 %a4, i32 %a5) #0 {
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b0:
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%v0 = bitcast i8* %a1 to i64*
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%v1 = load i64, i64* %v0, align 8, !tbaa !0
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%v2 = shl i64 %v1, 8
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%v3 = trunc i64 %v2 to i32
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%v4 = trunc i64 %v1 to i32
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%v5 = and i32 %v4, 16777215
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%v6 = bitcast i8* %a0 to <16 x i32>*
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%v7 = load <16 x i32>, <16 x i32>* %v6, align 64, !tbaa !4
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%v8 = getelementptr inbounds i8, i8* %a0, i32 32
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%v9 = bitcast i8* %v8 to <16 x i32>*
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%v10 = load <16 x i32>, <16 x i32>* %v9, align 64, !tbaa !4
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%v11 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v10, <16 x i32> %v7)
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%v12 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v11, i32 %v5, i32 0)
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%v13 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v11, i32 %v3, i32 0)
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%v14 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v12)
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%v15 = tail call <16 x i32> @llvm.hexagon.V6.vasrwuhsat(<16 x i32> %v14, <16 x i32> %v14, i32 %a2)
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%v16 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v13)
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%v17 = tail call <16 x i32> @llvm.hexagon.V6.vasrwuhsat(<16 x i32> %v16, <16 x i32> %v16, i32 %a2)
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%v18 = getelementptr inbounds i8, i8* %a3, i32 32
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%v19 = bitcast i8* %v18 to <16 x i32>*
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store <16 x i32> %v15, <16 x i32>* %v19, align 64, !tbaa !4
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%v20 = bitcast i8* %a3 to <16 x i32>*
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store <16 x i32> %v17, <16 x i32>* %v20, align 64, !tbaa !4
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32>, i32, i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vasrwuhsat(<16 x i32>, <16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
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; Function Attrs: nounwind readnone
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define i32 @f1() #2 {
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b0:
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ret i32 0
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"long long", !2, i64 0}
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!2 = !{!"omnipotent char", !3, i64 0}
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!3 = !{!"Simple C/C++ TBAA"}
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!4 = !{!2, !2, i64 0}
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