416 lines
12 KiB
LLVM
416 lines
12 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IFD %s
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; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IFD %s
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define i32 @fcmp_false(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fcmp_false:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: mv a0, zero
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fcmp_false:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: mv a0, zero
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; RV64IFD-NEXT: ret
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%1 = fcmp false double %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_oeq(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fcmp_oeq:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: feq.d a0, ft1, ft0
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fcmp_oeq:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.d.x ft0, a1
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; RV64IFD-NEXT: fmv.d.x ft1, a0
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; RV64IFD-NEXT: feq.d a0, ft1, ft0
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; RV64IFD-NEXT: ret
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%1 = fcmp oeq double %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_ogt(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fcmp_ogt:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: flt.d a0, ft1, ft0
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fcmp_ogt:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.d.x ft0, a0
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; RV64IFD-NEXT: fmv.d.x ft1, a1
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; RV64IFD-NEXT: flt.d a0, ft1, ft0
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; RV64IFD-NEXT: ret
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%1 = fcmp ogt double %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_oge(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fcmp_oge:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: fle.d a0, ft1, ft0
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fcmp_oge:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.d.x ft0, a0
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; RV64IFD-NEXT: fmv.d.x ft1, a1
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; RV64IFD-NEXT: fle.d a0, ft1, ft0
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; RV64IFD-NEXT: ret
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%1 = fcmp oge double %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_olt(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fcmp_olt:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: flt.d a0, ft1, ft0
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fcmp_olt:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.d.x ft0, a1
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; RV64IFD-NEXT: fmv.d.x ft1, a0
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; RV64IFD-NEXT: flt.d a0, ft1, ft0
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; RV64IFD-NEXT: ret
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%1 = fcmp olt double %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_ole(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fcmp_ole:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: fle.d a0, ft1, ft0
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fcmp_ole:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.d.x ft0, a1
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; RV64IFD-NEXT: fmv.d.x ft1, a0
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; RV64IFD-NEXT: fle.d a0, ft1, ft0
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; RV64IFD-NEXT: ret
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%1 = fcmp ole double %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_one(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fcmp_one:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: flt.d a0, ft1, ft0
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; RV32IFD-NEXT: flt.d a1, ft0, ft1
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; RV32IFD-NEXT: or a0, a1, a0
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fcmp_one:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.d.x ft0, a1
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; RV64IFD-NEXT: fmv.d.x ft1, a0
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; RV64IFD-NEXT: flt.d a0, ft1, ft0
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; RV64IFD-NEXT: flt.d a1, ft0, ft1
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; RV64IFD-NEXT: or a0, a1, a0
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; RV64IFD-NEXT: ret
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%1 = fcmp one double %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_ord(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fcmp_ord:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: feq.d a0, ft1, ft1
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; RV32IFD-NEXT: feq.d a1, ft0, ft0
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; RV32IFD-NEXT: and a0, a1, a0
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fcmp_ord:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.d.x ft0, a0
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; RV64IFD-NEXT: fmv.d.x ft1, a1
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; RV64IFD-NEXT: feq.d a0, ft1, ft1
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; RV64IFD-NEXT: feq.d a1, ft0, ft0
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; RV64IFD-NEXT: and a0, a1, a0
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; RV64IFD-NEXT: ret
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%1 = fcmp ord double %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_ueq(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fcmp_ueq:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: flt.d a0, ft1, ft0
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; RV32IFD-NEXT: flt.d a1, ft0, ft1
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; RV32IFD-NEXT: or a0, a1, a0
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; RV32IFD-NEXT: xori a0, a0, 1
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fcmp_ueq:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.d.x ft0, a1
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; RV64IFD-NEXT: fmv.d.x ft1, a0
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; RV64IFD-NEXT: flt.d a0, ft1, ft0
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; RV64IFD-NEXT: flt.d a1, ft0, ft1
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; RV64IFD-NEXT: or a0, a1, a0
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; RV64IFD-NEXT: xori a0, a0, 1
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; RV64IFD-NEXT: ret
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%1 = fcmp ueq double %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_ugt(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fcmp_ugt:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: fle.d a0, ft1, ft0
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; RV32IFD-NEXT: xori a0, a0, 1
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fcmp_ugt:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.d.x ft0, a1
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; RV64IFD-NEXT: fmv.d.x ft1, a0
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; RV64IFD-NEXT: fle.d a0, ft1, ft0
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; RV64IFD-NEXT: xori a0, a0, 1
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; RV64IFD-NEXT: ret
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%1 = fcmp ugt double %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_uge(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fcmp_uge:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: flt.d a0, ft1, ft0
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; RV32IFD-NEXT: xori a0, a0, 1
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fcmp_uge:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.d.x ft0, a1
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; RV64IFD-NEXT: fmv.d.x ft1, a0
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; RV64IFD-NEXT: flt.d a0, ft1, ft0
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; RV64IFD-NEXT: xori a0, a0, 1
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; RV64IFD-NEXT: ret
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%1 = fcmp uge double %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_ult(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fcmp_ult:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a2, 8(sp)
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|
|
; RV32IFD-NEXT: sw a3, 12(sp)
|
||
|
|
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||
|
|
; RV32IFD-NEXT: fle.d a0, ft1, ft0
|
||
|
|
; RV32IFD-NEXT: xori a0, a0, 1
|
||
|
|
; RV32IFD-NEXT: addi sp, sp, 16
|
||
|
|
; RV32IFD-NEXT: ret
|
||
|
|
;
|
||
|
|
; RV64IFD-LABEL: fcmp_ult:
|
||
|
|
; RV64IFD: # %bb.0:
|
||
|
|
; RV64IFD-NEXT: fmv.d.x ft0, a0
|
||
|
|
; RV64IFD-NEXT: fmv.d.x ft1, a1
|
||
|
|
; RV64IFD-NEXT: fle.d a0, ft1, ft0
|
||
|
|
; RV64IFD-NEXT: xori a0, a0, 1
|
||
|
|
; RV64IFD-NEXT: ret
|
||
|
|
%1 = fcmp ult double %a, %b
|
||
|
|
%2 = zext i1 %1 to i32
|
||
|
|
ret i32 %2
|
||
|
|
}
|
||
|
|
|
||
|
|
define i32 @fcmp_ule(double %a, double %b) nounwind {
|
||
|
|
; RV32IFD-LABEL: fcmp_ule:
|
||
|
|
; RV32IFD: # %bb.0:
|
||
|
|
; RV32IFD-NEXT: addi sp, sp, -16
|
||
|
|
; RV32IFD-NEXT: sw a0, 8(sp)
|
||
|
|
; RV32IFD-NEXT: sw a1, 12(sp)
|
||
|
|
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||
|
|
; RV32IFD-NEXT: sw a2, 8(sp)
|
||
|
|
; RV32IFD-NEXT: sw a3, 12(sp)
|
||
|
|
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||
|
|
; RV32IFD-NEXT: flt.d a0, ft1, ft0
|
||
|
|
; RV32IFD-NEXT: xori a0, a0, 1
|
||
|
|
; RV32IFD-NEXT: addi sp, sp, 16
|
||
|
|
; RV32IFD-NEXT: ret
|
||
|
|
;
|
||
|
|
; RV64IFD-LABEL: fcmp_ule:
|
||
|
|
; RV64IFD: # %bb.0:
|
||
|
|
; RV64IFD-NEXT: fmv.d.x ft0, a0
|
||
|
|
; RV64IFD-NEXT: fmv.d.x ft1, a1
|
||
|
|
; RV64IFD-NEXT: flt.d a0, ft1, ft0
|
||
|
|
; RV64IFD-NEXT: xori a0, a0, 1
|
||
|
|
; RV64IFD-NEXT: ret
|
||
|
|
%1 = fcmp ule double %a, %b
|
||
|
|
%2 = zext i1 %1 to i32
|
||
|
|
ret i32 %2
|
||
|
|
}
|
||
|
|
|
||
|
|
define i32 @fcmp_une(double %a, double %b) nounwind {
|
||
|
|
; RV32IFD-LABEL: fcmp_une:
|
||
|
|
; RV32IFD: # %bb.0:
|
||
|
|
; RV32IFD-NEXT: addi sp, sp, -16
|
||
|
|
; RV32IFD-NEXT: sw a2, 8(sp)
|
||
|
|
; RV32IFD-NEXT: sw a3, 12(sp)
|
||
|
|
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||
|
|
; RV32IFD-NEXT: sw a0, 8(sp)
|
||
|
|
; RV32IFD-NEXT: sw a1, 12(sp)
|
||
|
|
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||
|
|
; RV32IFD-NEXT: feq.d a0, ft1, ft0
|
||
|
|
; RV32IFD-NEXT: xori a0, a0, 1
|
||
|
|
; RV32IFD-NEXT: addi sp, sp, 16
|
||
|
|
; RV32IFD-NEXT: ret
|
||
|
|
;
|
||
|
|
; RV64IFD-LABEL: fcmp_une:
|
||
|
|
; RV64IFD: # %bb.0:
|
||
|
|
; RV64IFD-NEXT: fmv.d.x ft0, a1
|
||
|
|
; RV64IFD-NEXT: fmv.d.x ft1, a0
|
||
|
|
; RV64IFD-NEXT: feq.d a0, ft1, ft0
|
||
|
|
; RV64IFD-NEXT: xori a0, a0, 1
|
||
|
|
; RV64IFD-NEXT: ret
|
||
|
|
%1 = fcmp une double %a, %b
|
||
|
|
%2 = zext i1 %1 to i32
|
||
|
|
ret i32 %2
|
||
|
|
}
|
||
|
|
|
||
|
|
define i32 @fcmp_uno(double %a, double %b) nounwind {
|
||
|
|
; RV32IFD-LABEL: fcmp_uno:
|
||
|
|
; RV32IFD: # %bb.0:
|
||
|
|
; RV32IFD-NEXT: addi sp, sp, -16
|
||
|
|
; RV32IFD-NEXT: sw a0, 8(sp)
|
||
|
|
; RV32IFD-NEXT: sw a1, 12(sp)
|
||
|
|
; RV32IFD-NEXT: fld ft0, 8(sp)
|
||
|
|
; RV32IFD-NEXT: sw a2, 8(sp)
|
||
|
|
; RV32IFD-NEXT: sw a3, 12(sp)
|
||
|
|
; RV32IFD-NEXT: fld ft1, 8(sp)
|
||
|
|
; RV32IFD-NEXT: feq.d a0, ft1, ft1
|
||
|
|
; RV32IFD-NEXT: feq.d a1, ft0, ft0
|
||
|
|
; RV32IFD-NEXT: and a0, a1, a0
|
||
|
|
; RV32IFD-NEXT: xori a0, a0, 1
|
||
|
|
; RV32IFD-NEXT: addi sp, sp, 16
|
||
|
|
; RV32IFD-NEXT: ret
|
||
|
|
;
|
||
|
|
; RV64IFD-LABEL: fcmp_uno:
|
||
|
|
; RV64IFD: # %bb.0:
|
||
|
|
; RV64IFD-NEXT: fmv.d.x ft0, a0
|
||
|
|
; RV64IFD-NEXT: fmv.d.x ft1, a1
|
||
|
|
; RV64IFD-NEXT: feq.d a0, ft1, ft1
|
||
|
|
; RV64IFD-NEXT: feq.d a1, ft0, ft0
|
||
|
|
; RV64IFD-NEXT: and a0, a1, a0
|
||
|
|
; RV64IFD-NEXT: xori a0, a0, 1
|
||
|
|
; RV64IFD-NEXT: ret
|
||
|
|
%1 = fcmp uno double %a, %b
|
||
|
|
%2 = zext i1 %1 to i32
|
||
|
|
ret i32 %2
|
||
|
|
}
|
||
|
|
|
||
|
|
define i32 @fcmp_true(double %a, double %b) nounwind {
|
||
|
|
; RV32IFD-LABEL: fcmp_true:
|
||
|
|
; RV32IFD: # %bb.0:
|
||
|
|
; RV32IFD-NEXT: addi a0, zero, 1
|
||
|
|
; RV32IFD-NEXT: ret
|
||
|
|
;
|
||
|
|
; RV64IFD-LABEL: fcmp_true:
|
||
|
|
; RV64IFD: # %bb.0:
|
||
|
|
; RV64IFD-NEXT: addi a0, zero, 1
|
||
|
|
; RV64IFD-NEXT: ret
|
||
|
|
%1 = fcmp true double %a, %b
|
||
|
|
%2 = zext i1 %1 to i32
|
||
|
|
ret i32 %2
|
||
|
|
}
|