133 lines
3.6 KiB
Plaintext
133 lines
3.6 KiB
Plaintext
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# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefix=RV32I-MO %s
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# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefix=RV64I-MO %s
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--- |
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define i32 @outline_0(i32 %a, i32 %b) { ret i32 0 }
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define i32 @outline_1(i32 %a, i32 %b) { ret i32 0 }
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define i32 @outline_2(i32 %a, i32 %b) { ret i32 0 }
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; Should not outline linkonce_odr functions which could be deduplicated by the
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; linker.
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define linkonce_odr i32 @dont_outline_0(i32 %a, i32 %b) { ret i32 0 }
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; Should not outline functions with named linker sections
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define i32 @dont_outline_1(i32 %a, i32 %b) section "named" { ret i32 0 }
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; Cannot outline if the X5 (t0) register is not free
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define i32 @dont_outline_2(i32 %a, i32 %b) { ret i32 0 }
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...
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---
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name: outline_0
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: outline_0
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; RV32I-MO: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
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;
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; RV64I-MO-LABEL: name: outline_0
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; RV64I-MO: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
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$x11 = ORI $x11, 1023
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$x12 = ADDI $x10, 17
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$x11 = AND $x12, $x11
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$x10 = SUB $x10, $x11
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PseudoRET implicit $x10
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...
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---
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name: outline_1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: outline_1
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; RV32I-MO: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
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;
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; RV64I-MO-LABEL: name: outline_1
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; RV64I-MO: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
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$x11 = ORI $x11, 1023
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$x12 = ADDI $x10, 17
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$x11 = AND $x12, $x11
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$x10 = SUB $x10, $x11
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PseudoRET implicit $x10
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...
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---
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name: outline_2
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: outline_2
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; RV32I-MO: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
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;
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; RV64I-MO-LABEL: name: outline_2
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; RV64I-MO: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
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$x11 = ORI $x11, 1023
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$x12 = ADDI $x10, 17
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$x11 = AND $x12, $x11
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$x10 = SUB $x10, $x11
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PseudoRET implicit $x10
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...
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---
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name: dont_outline_0
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: dont_outline_0
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; RV32I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
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;
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; RV64I-MO-LABEL: name: dont_outline_0
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; RV64I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
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$x11 = ORI $x11, 1023
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$x12 = ADDI $x10, 17
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$x11 = AND $x12, $x11
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$x10 = SUB $x10, $x11
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PseudoRET implicit $x10
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...
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---
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name: dont_outline_1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: dont_outline_1
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; RV32I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
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;
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; RV64I-MO-LABEL: name: dont_outline_1
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; RV64I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
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$x11 = ORI $x11, 1023
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$x12 = ADDI $x10, 17
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$x11 = AND $x12, $x11
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$x10 = SUB $x10, $x11
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PseudoRET implicit $x10
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...
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---
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name: dont_outline_2
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11, $x5
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; RV32I-MO-LABEL: name: dont_outline_2
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; RV32I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
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;
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; RV64I-MO-LABEL: name: dont_outline_2
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; RV64I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
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$x11 = ORI $x11, 1023
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$x12 = ADDI $x10, 17
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$x11 = AND $x12, $x11
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$x10 = SUB $x10, $x11
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$x10 = ADD $x10, $x5
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PseudoRET implicit $x10
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...
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