235 lines
8.7 KiB
Plaintext
235 lines
8.7 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -o - -mtriple=x86_64-- -run-pass=twoaddressinstruction,simple-register-coalescing %s | FileCheck %s
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# Tests for commuting ADCX and ADOX to avoid copies. The ADOX tests were manually constructed by modifying ADCX tests to use OF instead of CF.
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--- |
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; ModuleID = 'test.ll'
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source_filename = "test.ll"
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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define void @adcx32_commute(i8 %cf, i32 %a, i32 %b, i32* %res) #0 {
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%ret = call { i8, i32 } @llvm.x86.addcarry.32(i8 %cf, i32 %a, i32 %b)
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%1 = extractvalue { i8, i32 } %ret, 1
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%2 = mul i32 %a, %1
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store i32 %2, i32* %res
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ret void
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}
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define void @adcx64_commute(i8 %cf, i64 %a, i64 %b, i64* %res) #0 {
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%ret = call { i8, i64 } @llvm.x86.addcarry.64(i8 %cf, i64 %a, i64 %b)
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%1 = extractvalue { i8, i64 } %ret, 1
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%2 = mul i64 %a, %1
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store i64 %2, i64* %res
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ret void
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}
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define void @adox32_commute(i8 %cf, i32 %a, i32 %b, i32* %res) #0 {
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%ret = call { i8, i32 } @llvm.x86.addcarry.32(i8 %cf, i32 %a, i32 %b)
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%1 = extractvalue { i8, i32 } %ret, 1
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%2 = mul i32 %a, %1
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store i32 %2, i32* %res
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ret void
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}
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define void @adox64_commute(i8 %cf, i64 %a, i64 %b, i64* %res) #0 {
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%ret = call { i8, i64 } @llvm.x86.addcarry.64(i8 %cf, i64 %a, i64 %b)
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%1 = extractvalue { i8, i64 } %ret, 1
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%2 = mul i64 %a, %1
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store i64 %2, i64* %res
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ret void
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}
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; Function Attrs: nounwind readnone
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declare { i8, i32 } @llvm.x86.addcarry.32(i8, i32, i32) #1
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; Function Attrs: nounwind readnone
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declare { i8, i64 } @llvm.x86.addcarry.64(i8, i64, i64) #1
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; Function Attrs: nounwind
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declare void @llvm.stackprotector(i8*, i8**) #2
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attributes #0 = { "target-features"="+adx" }
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attributes #1 = { nounwind readnone "target-features"="+adx" }
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attributes #2 = { nounwind }
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...
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---
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name: adcx32_commute
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alignment: 16
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr32 }
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- { id: 1, class: gr32 }
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- { id: 2, class: gr32 }
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- { id: 3, class: gr64 }
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- { id: 4, class: gr8 }
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- { id: 5, class: gr8 }
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- { id: 6, class: gr32 }
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- { id: 7, class: gr32 }
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liveins:
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- { reg: '$edi', virtual-reg: '%0' }
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- { reg: '$esi', virtual-reg: '%1' }
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- { reg: '$edx', virtual-reg: '%2' }
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- { reg: '$rcx', virtual-reg: '%3' }
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body: |
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bb.0 (%ir-block.0):
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liveins: $edi, $esi, $edx, $rcx
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; CHECK-LABEL: name: adcx32_commute
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; CHECK: liveins: $edi, $esi, $edx, $rcx
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; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rcx
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; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $edx
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; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
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; CHECK: [[COPY3:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: dead [[COPY3]].sub_8bit:gr32 = ADD8ri [[COPY3]].sub_8bit, -1, implicit-def $eflags
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; CHECK: [[ADCX32rr:%[0-9]+]]:gr32 = ADCX32rr [[ADCX32rr]], [[COPY2]], implicit-def dead $eflags, implicit killed $eflags
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; CHECK: [[IMUL32rr:%[0-9]+]]:gr32 = IMUL32rr [[IMUL32rr]], [[COPY2]], implicit-def dead $eflags
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; CHECK: MOV32mr [[COPY]], 1, $noreg, 0, $noreg, [[IMUL32rr]] :: (store 4 into %ir.res)
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; CHECK: RET 0
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%3:gr64 = COPY killed $rcx
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%2:gr32 = COPY killed $edx
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%1:gr32 = COPY killed $esi
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%0:gr32 = COPY killed $edi
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%4:gr8 = COPY killed %0.sub_8bit
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dead %5:gr8 = ADD8ri killed %4, -1, implicit-def $eflags
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%6:gr32 = ADCX32rr %1, killed %2, implicit-def dead $eflags, implicit killed $eflags
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%7:gr32 = IMUL32rr killed %1, killed %6, implicit-def dead $eflags
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MOV32mr killed %3, 1, $noreg, 0, $noreg, killed %7 :: (store 4 into %ir.res)
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RET 0
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...
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---
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name: adcx64_commute
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alignment: 16
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr32 }
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- { id: 1, class: gr64 }
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- { id: 2, class: gr64 }
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- { id: 3, class: gr64 }
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- { id: 4, class: gr8 }
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- { id: 5, class: gr8 }
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- { id: 6, class: gr64 }
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- { id: 7, class: gr64 }
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liveins:
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- { reg: '$edi', virtual-reg: '%0' }
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- { reg: '$rsi', virtual-reg: '%1' }
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- { reg: '$rdx', virtual-reg: '%2' }
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- { reg: '$rcx', virtual-reg: '%3' }
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body: |
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bb.0 (%ir-block.0):
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liveins: $edi, $rsi, $rdx, $rcx
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; CHECK-LABEL: name: adcx64_commute
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; CHECK: liveins: $edi, $rsi, $rdx, $rcx
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; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rcx
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; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY $rdx
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; CHECK: [[COPY2:%[0-9]+]]:gr64 = COPY $rsi
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; CHECK: [[COPY3:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: dead [[COPY3]].sub_8bit:gr32 = ADD8ri [[COPY3]].sub_8bit, -1, implicit-def $eflags
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; CHECK: [[ADCX64rr:%[0-9]+]]:gr64 = ADCX64rr [[ADCX64rr]], [[COPY2]], implicit-def dead $eflags, implicit killed $eflags
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; CHECK: [[IMUL64rr:%[0-9]+]]:gr64 = IMUL64rr [[IMUL64rr]], [[COPY2]], implicit-def dead $eflags
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; CHECK: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[IMUL64rr]] :: (store 8 into %ir.res)
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; CHECK: RET 0
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%3:gr64 = COPY killed $rcx
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%2:gr64 = COPY killed $rdx
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%1:gr64 = COPY killed $rsi
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%0:gr32 = COPY killed $edi
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%4:gr8 = COPY killed %0.sub_8bit
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dead %5:gr8 = ADD8ri killed %4, -1, implicit-def $eflags
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%6:gr64 = ADCX64rr %1, killed %2, implicit-def dead $eflags, implicit killed $eflags
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%7:gr64 = IMUL64rr killed %1, killed %6, implicit-def dead $eflags
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MOV64mr killed %3, 1, $noreg, 0, $noreg, killed %7 :: (store 8 into %ir.res)
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RET 0
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...
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---
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name: adox32_commute
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alignment: 16
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr32 }
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- { id: 1, class: gr32 }
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- { id: 2, class: gr32 }
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- { id: 3, class: gr64 }
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- { id: 4, class: gr8 }
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- { id: 5, class: gr8 }
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- { id: 6, class: gr32 }
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- { id: 7, class: gr32 }
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liveins:
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- { reg: '$edi', virtual-reg: '%0' }
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- { reg: '$esi', virtual-reg: '%1' }
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- { reg: '$edx', virtual-reg: '%2' }
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- { reg: '$rcx', virtual-reg: '%3' }
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body: |
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bb.0 (%ir-block.0):
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liveins: $edi, $esi, $edx, $rcx
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; CHECK-LABEL: name: adox32_commute
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; CHECK: liveins: $edi, $esi, $edx, $rcx
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; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rcx
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; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $edx
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; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
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; CHECK: [[COPY3:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: dead [[COPY3]].sub_8bit:gr32 = ADD8ri [[COPY3]].sub_8bit, 127, implicit-def $eflags
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; CHECK: [[ADOX32rr:%[0-9]+]]:gr32 = ADOX32rr [[ADOX32rr]], [[COPY2]], implicit-def dead $eflags, implicit killed $eflags
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; CHECK: [[IMUL32rr:%[0-9]+]]:gr32 = IMUL32rr [[IMUL32rr]], [[COPY2]], implicit-def dead $eflags
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; CHECK: MOV32mr [[COPY]], 1, $noreg, 0, $noreg, [[IMUL32rr]] :: (store 4 into %ir.res)
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; CHECK: RET 0
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%3:gr64 = COPY killed $rcx
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%2:gr32 = COPY killed $edx
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%1:gr32 = COPY killed $esi
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%0:gr32 = COPY killed $edi
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%4:gr8 = COPY killed %0.sub_8bit
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dead %5:gr8 = ADD8ri killed %4, 127, implicit-def $eflags
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%6:gr32 = ADOX32rr %1, killed %2, implicit-def dead $eflags, implicit killed $eflags
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%7:gr32 = IMUL32rr killed %1, killed %6, implicit-def dead $eflags
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MOV32mr killed %3, 1, $noreg, 0, $noreg, killed %7 :: (store 4 into %ir.res)
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RET 0
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...
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---
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name: adox64_commute
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alignment: 16
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr32 }
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- { id: 1, class: gr64 }
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- { id: 2, class: gr64 }
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- { id: 3, class: gr64 }
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- { id: 4, class: gr8 }
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- { id: 5, class: gr8 }
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- { id: 6, class: gr64 }
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- { id: 7, class: gr64 }
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liveins:
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- { reg: '$edi', virtual-reg: '%0' }
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- { reg: '$rsi', virtual-reg: '%1' }
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- { reg: '$rdx', virtual-reg: '%2' }
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- { reg: '$rcx', virtual-reg: '%3' }
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body: |
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bb.0 (%ir-block.0):
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liveins: $edi, $rsi, $rdx, $rcx
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; CHECK-LABEL: name: adox64_commute
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; CHECK: liveins: $edi, $rsi, $rdx, $rcx
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; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rcx
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; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY $rdx
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; CHECK: [[COPY2:%[0-9]+]]:gr64 = COPY $rsi
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; CHECK: [[COPY3:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: dead [[COPY3]].sub_8bit:gr32 = ADD8ri [[COPY3]].sub_8bit, 127, implicit-def $eflags
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; CHECK: [[ADOX64rr:%[0-9]+]]:gr64 = ADOX64rr [[ADOX64rr]], [[COPY2]], implicit-def dead $eflags, implicit killed $eflags
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; CHECK: [[IMUL64rr:%[0-9]+]]:gr64 = IMUL64rr [[IMUL64rr]], [[COPY2]], implicit-def dead $eflags
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; CHECK: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[IMUL64rr]] :: (store 8 into %ir.res)
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; CHECK: RET 0
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%3:gr64 = COPY killed $rcx
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%2:gr64 = COPY killed $rdx
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%1:gr64 = COPY killed $rsi
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%0:gr32 = COPY killed $edi
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%4:gr8 = COPY killed %0.sub_8bit
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dead %5:gr8 = ADD8ri killed %4, 127, implicit-def $eflags
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%6:gr64 = ADOX64rr %1, killed %2, implicit-def dead $eflags, implicit killed $eflags
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%7:gr64 = IMUL64rr killed %1, killed %6, implicit-def dead $eflags
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MOV64mr killed %3, 1, $noreg, 0, $noreg, killed %7 :: (store 8 into %ir.res)
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RET 0
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...
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