303 lines
11 KiB
LLVM
303 lines
11 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32-SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefixes=X64,X64-SSSE3
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefixes=X64,X64-AVX
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=X64,X64-AVX
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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define i32 @t(<2 x i64>* %val) nounwind {
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; X32-SSE2-LABEL: t:
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; X32-SSE2: # %bb.0:
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; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE2-NEXT: pshufd {{.*#+}} xmm0 = mem[2,3,2,3]
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; X32-SSE2-NEXT: movd %xmm0, %eax
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; X32-SSE2-NEXT: retl
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;
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; X64-SSSE3-LABEL: t:
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; X64-SSSE3: # %bb.0:
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; X64-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = mem[2,3,2,3]
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; X64-SSSE3-NEXT: movd %xmm0, %eax
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; X64-SSSE3-NEXT: retq
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;
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; X64-AVX-LABEL: t:
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; X64-AVX: # %bb.0:
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; X64-AVX-NEXT: movl 8(%rdi), %eax
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; X64-AVX-NEXT: retq
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%tmp2 = load <2 x i64>, <2 x i64>* %val, align 16 ; <<2 x i64>> [#uses=1]
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%tmp3 = bitcast <2 x i64> %tmp2 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%tmp4 = extractelement <4 x i32> %tmp3, i32 2 ; <i32> [#uses=1]
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ret i32 %tmp4
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}
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; Case where extractelement of load ends up as undef.
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; (Making sure this doesn't crash.)
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define i32 @t2(<8 x i32>* %xp) {
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; X32-SSE2-LABEL: t2:
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; X32-SSE2: # %bb.0:
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; X32-SSE2-NEXT: retl
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;
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; X64-LABEL: t2:
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; X64: # %bb.0:
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; X64-NEXT: retq
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%x = load <8 x i32>, <8 x i32>* %xp
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%Shuff68 = shufflevector <8 x i32> %x, <8 x i32> undef, <8 x i32> <i32 undef, i32 7, i32 9, i32 undef, i32 13, i32 15, i32 1, i32 3>
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%y = extractelement <8 x i32> %Shuff68, i32 0
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ret i32 %y
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}
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; This case could easily end up inf-looping in the DAG combiner due to an
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; low alignment load of the vector which prevents us from reliably forming a
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; narrow load.
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define void @t3(<2 x double>* %a0) {
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; X32-SSE2-LABEL: t3:
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; X32-SSE2: # %bb.0: # %bb
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; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE2-NEXT: movups (%eax), %xmm0
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; X32-SSE2-NEXT: movhps %xmm0, (%eax)
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; X32-SSE2-NEXT: retl
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;
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; X64-SSSE3-LABEL: t3:
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; X64-SSSE3: # %bb.0: # %bb
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; X64-SSSE3-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X64-SSSE3-NEXT: movsd %xmm0, (%rax)
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; X64-SSSE3-NEXT: retq
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;
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; X64-AVX-LABEL: t3:
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; X64-AVX: # %bb.0: # %bb
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; X64-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; X64-AVX-NEXT: vmovsd %xmm0, (%rax)
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; X64-AVX-NEXT: retq
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bb:
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%tmp13 = load <2 x double>, <2 x double>* %a0, align 1
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%.sroa.3.24.vec.extract = extractelement <2 x double> %tmp13, i32 1
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store double %.sroa.3.24.vec.extract, double* undef, align 8
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ret void
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}
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; Case where a load is unary shuffled, then bitcast (to a type with the same
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; number of elements) before extractelement.
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; This is testing for an assertion - the extraction was assuming that the undef
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; second shuffle operand was a post-bitcast type instead of a pre-bitcast type.
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define i64 @t4(<2 x double>* %a) {
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; X32-SSE2-LABEL: t4:
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; X32-SSE2: # %bb.0:
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; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE2-NEXT: movdqa (%eax), %xmm0
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; X32-SSE2-NEXT: movd %xmm0, %eax
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; X32-SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
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; X32-SSE2-NEXT: movd %xmm0, %edx
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; X32-SSE2-NEXT: retl
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;
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; X64-LABEL: t4:
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; X64: # %bb.0:
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; X64-NEXT: movq (%rdi), %rax
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; X64-NEXT: retq
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%b = load <2 x double>, <2 x double>* %a, align 16
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%c = shufflevector <2 x double> %b, <2 x double> %b, <2 x i32> <i32 1, i32 0>
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%d = bitcast <2 x double> %c to <2 x i64>
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%e = extractelement <2 x i64> %d, i32 1
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ret i64 %e
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}
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; Don't extract from a volatile.
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define void @t5(<2 x double> *%a0, double *%a1) {
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; X32-SSE2-LABEL: t5:
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; X32-SSE2: # %bb.0:
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; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-SSE2-NEXT: movaps (%ecx), %xmm0
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; X32-SSE2-NEXT: movhps %xmm0, (%eax)
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; X32-SSE2-NEXT: retl
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;
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; X64-SSSE3-LABEL: t5:
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; X64-SSSE3: # %bb.0:
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; X64-SSSE3-NEXT: movaps (%rdi), %xmm0
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; X64-SSSE3-NEXT: movhps %xmm0, (%rsi)
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; X64-SSSE3-NEXT: retq
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;
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; X64-AVX-LABEL: t5:
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; X64-AVX: # %bb.0:
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; X64-AVX-NEXT: vmovaps (%rdi), %xmm0
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; X64-AVX-NEXT: vmovhps %xmm0, (%rsi)
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; X64-AVX-NEXT: retq
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%vecload = load volatile <2 x double>, <2 x double>* %a0, align 16
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%vecext = extractelement <2 x double> %vecload, i32 1
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store volatile double %vecext, double* %a1, align 8
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ret void
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}
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; Check for multiuse.
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define float @t6(<8 x float> *%a0) {
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; X32-SSE2-LABEL: t6:
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; X32-SSE2: # %bb.0:
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; X32-SSE2-NEXT: pushl %eax
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; X32-SSE2-NEXT: .cfi_def_cfa_offset 8
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; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE2-NEXT: movaps (%eax), %xmm0
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; X32-SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
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; X32-SSE2-NEXT: xorps %xmm1, %xmm1
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; X32-SSE2-NEXT: cmpeqss %xmm0, %xmm1
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; X32-SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; X32-SSE2-NEXT: andps %xmm1, %xmm2
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; X32-SSE2-NEXT: andnps %xmm0, %xmm1
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; X32-SSE2-NEXT: orps %xmm2, %xmm1
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; X32-SSE2-NEXT: movss %xmm1, (%esp)
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; X32-SSE2-NEXT: flds (%esp)
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; X32-SSE2-NEXT: popl %eax
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; X32-SSE2-NEXT: .cfi_def_cfa_offset 4
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; X32-SSE2-NEXT: retl
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;
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; X64-SSSE3-LABEL: t6:
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; X64-SSSE3: # %bb.0:
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; X64-SSSE3-NEXT: movshdup {{.*#+}} xmm1 = mem[1,1,3,3]
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; X64-SSSE3-NEXT: xorps %xmm0, %xmm0
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; X64-SSSE3-NEXT: cmpeqss %xmm1, %xmm0
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; X64-SSSE3-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; X64-SSSE3-NEXT: andps %xmm0, %xmm2
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; X64-SSSE3-NEXT: andnps %xmm1, %xmm0
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; X64-SSSE3-NEXT: orps %xmm2, %xmm0
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; X64-SSSE3-NEXT: retq
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;
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; X64-AVX-LABEL: t6:
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; X64-AVX: # %bb.0:
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; X64-AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X64-AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; X64-AVX-NEXT: vcmpeqss %xmm1, %xmm0, %xmm1
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; X64-AVX-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; X64-AVX-NEXT: vblendvps %xmm1, %xmm2, %xmm0, %xmm0
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; X64-AVX-NEXT: retq
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%vecload = load <8 x float>, <8 x float>* %a0, align 32
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%vecext = extractelement <8 x float> %vecload, i32 1
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%cmp = fcmp oeq float %vecext, 0.000000e+00
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%cond = select i1 %cmp, float 1.000000e+00, float %vecext
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ret float %cond
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}
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define void @PR43971(<8 x float> *%a0, float *%a1) {
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; X32-SSE2-LABEL: PR43971:
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; X32-SSE2: # %bb.0: # %entry
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; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-SSE2-NEXT: movaps 16(%ecx), %xmm0
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; X32-SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
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; X32-SSE2-NEXT: xorps %xmm1, %xmm1
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; X32-SSE2-NEXT: cmpltss %xmm0, %xmm1
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; X32-SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; X32-SSE2-NEXT: andps %xmm1, %xmm2
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; X32-SSE2-NEXT: andnps %xmm0, %xmm1
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; X32-SSE2-NEXT: orps %xmm2, %xmm1
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; X32-SSE2-NEXT: movss %xmm1, (%eax)
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; X32-SSE2-NEXT: retl
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;
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; X64-SSSE3-LABEL: PR43971:
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; X64-SSSE3: # %bb.0: # %entry
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; X64-SSSE3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X64-SSSE3-NEXT: xorps %xmm1, %xmm1
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; X64-SSSE3-NEXT: cmpltss %xmm0, %xmm1
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; X64-SSSE3-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; X64-SSSE3-NEXT: andps %xmm1, %xmm2
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; X64-SSSE3-NEXT: andnps %xmm0, %xmm1
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; X64-SSSE3-NEXT: orps %xmm2, %xmm1
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; X64-SSSE3-NEXT: movss %xmm1, (%rsi)
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; X64-SSSE3-NEXT: retq
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;
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; X64-AVX-LABEL: PR43971:
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; X64-AVX: # %bb.0: # %entry
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; X64-AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X64-AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; X64-AVX-NEXT: vcmpltss %xmm0, %xmm1, %xmm1
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; X64-AVX-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; X64-AVX-NEXT: vblendvps %xmm1, %xmm2, %xmm0, %xmm0
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; X64-AVX-NEXT: vmovss %xmm0, (%rsi)
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; X64-AVX-NEXT: retq
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entry:
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%0 = load <8 x float>, <8 x float>* %a0, align 32
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%vecext = extractelement <8 x float> %0, i32 6
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%cmp = fcmp ogt float %vecext, 0.000000e+00
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%1 = load float, float* %a1, align 4
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%cond = select i1 %cmp, float %1, float %vecext
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store float %cond, float* %a1, align 4
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ret void
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}
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define float @PR43971_1(<8 x float> *%a0) nounwind {
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; X32-SSE2-LABEL: PR43971_1:
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; X32-SSE2: # %bb.0: # %entry
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; X32-SSE2-NEXT: pushl %eax
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; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE2-NEXT: movaps (%eax), %xmm0
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; X32-SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
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; X32-SSE2-NEXT: xorps %xmm1, %xmm1
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; X32-SSE2-NEXT: cmpeqss %xmm0, %xmm1
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; X32-SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; X32-SSE2-NEXT: andps %xmm1, %xmm2
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; X32-SSE2-NEXT: andnps %xmm0, %xmm1
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; X32-SSE2-NEXT: orps %xmm2, %xmm1
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; X32-SSE2-NEXT: movss %xmm1, (%esp)
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; X32-SSE2-NEXT: flds (%esp)
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; X32-SSE2-NEXT: popl %eax
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; X32-SSE2-NEXT: retl
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;
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; X64-SSSE3-LABEL: PR43971_1:
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; X64-SSSE3: # %bb.0: # %entry
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; X64-SSSE3-NEXT: movshdup {{.*#+}} xmm1 = mem[1,1,3,3]
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; X64-SSSE3-NEXT: xorps %xmm0, %xmm0
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; X64-SSSE3-NEXT: cmpeqss %xmm1, %xmm0
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; X64-SSSE3-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; X64-SSSE3-NEXT: andps %xmm0, %xmm2
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; X64-SSSE3-NEXT: andnps %xmm1, %xmm0
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; X64-SSSE3-NEXT: orps %xmm2, %xmm0
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; X64-SSSE3-NEXT: retq
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;
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; X64-AVX-LABEL: PR43971_1:
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; X64-AVX: # %bb.0: # %entry
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; X64-AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X64-AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; X64-AVX-NEXT: vcmpeqss %xmm1, %xmm0, %xmm1
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; X64-AVX-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; X64-AVX-NEXT: vblendvps %xmm1, %xmm2, %xmm0, %xmm0
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; X64-AVX-NEXT: retq
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entry:
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%0 = load <8 x float>, <8 x float>* %a0, align 32
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%vecext = extractelement <8 x float> %0, i32 1
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%cmp = fcmp oeq float %vecext, 0.000000e+00
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%cond = select i1 %cmp, float 1.000000e+00, float %vecext
|
||
|
|
ret float %cond
|
||
|
|
}
|
||
|
|
|
||
|
|
; Test for bad extractions from a VBROADCAST_LOAD of the <2 x i16> non-uniform constant bitcast as <4 x i32>.
|
||
|
|
define void @subextract_broadcast_load_constant(<2 x i16>* nocapture %0, i16* nocapture %1, i16* nocapture %2) {
|
||
|
|
; X32-SSE2-LABEL: subextract_broadcast_load_constant:
|
||
|
|
; X32-SSE2: # %bb.0:
|
||
|
|
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||
|
|
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||
|
|
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %edx
|
||
|
|
; X32-SSE2-NEXT: movl $-1583308898, (%edx) # imm = 0xA1A09F9E
|
||
|
|
; X32-SSE2-NEXT: movw $-24674, (%ecx) # imm = 0x9F9E
|
||
|
|
; X32-SSE2-NEXT: movw $-24160, (%eax) # imm = 0xA1A0
|
||
|
|
; X32-SSE2-NEXT: retl
|
||
|
|
;
|
||
|
|
; X64-LABEL: subextract_broadcast_load_constant:
|
||
|
|
; X64: # %bb.0:
|
||
|
|
; X64-NEXT: movl $-1583308898, (%rdi) # imm = 0xA1A09F9E
|
||
|
|
; X64-NEXT: movw $-24674, (%rsi) # imm = 0x9F9E
|
||
|
|
; X64-NEXT: movw $-24160, (%rdx) # imm = 0xA1A0
|
||
|
|
; X64-NEXT: retq
|
||
|
|
%4 = bitcast <2 x i16>* %0 to i8*
|
||
|
|
store i8 -98, i8* %4, align 1
|
||
|
|
%5 = getelementptr inbounds i8, i8* %4, i64 1
|
||
|
|
store i8 -97, i8* %5, align 1
|
||
|
|
%6 = getelementptr inbounds i8, i8* %4, i64 2
|
||
|
|
store i8 -96, i8* %6, align 1
|
||
|
|
%7 = getelementptr inbounds i8, i8* %4, i64 3
|
||
|
|
store i8 -95, i8* %7, align 1
|
||
|
|
%8 = load <2 x i16>, <2 x i16>* %0, align 4
|
||
|
|
%9 = extractelement <2 x i16> %8, i32 0
|
||
|
|
store i16 %9, i16* %1, align 2
|
||
|
|
%10 = extractelement <2 x i16> %8, i32 1
|
||
|
|
store i16 %10, i16* %2, align 2
|
||
|
|
ret void
|
||
|
|
}
|