200 lines
8.0 KiB
LLVM
200 lines
8.0 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-apple-darwin -fast-isel -code-model=small < %s | FileCheck %s
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; RUN: llc -mtriple=x86_64-apple-darwin -fast-isel -code-model=large < %s | FileCheck %s --check-prefix=LARGE
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; RUN: llc -mtriple=x86_64 -fast-isel -code-model=large -relocation-model=pic < %s | FileCheck %s --check-prefix=LARGE_PIC
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; RUN: llc -mtriple=x86_64-apple-darwin -fast-isel -code-model=small -mattr=avx < %s | FileCheck %s --check-prefix=AVX
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; RUN: llc -mtriple=x86_64-apple-darwin -fast-isel -code-model=large -mattr=avx < %s | FileCheck %s --check-prefix=LARGE_AVX
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; RUN: llc -mtriple=x86_64-apple-darwin -fast-isel -code-model=small -mattr=avx512f < %s | FileCheck %s --check-prefix=AVX
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; RUN: llc -mtriple=x86_64-apple-darwin -fast-isel -code-model=large -mattr=avx512f < %s | FileCheck %s --check-prefix=LARGE_AVX
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; This large code mode shouldn't mean anything on x86 but it used to
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; generate 64-bit only instructions and asserted in the encoder.
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; -show-mc-encoding here to assert if this breaks again.
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; RUN: llc -mtriple=i686-apple-darwin -fast-isel -code-model=large -mattr=sse2 -show-mc-encoding < %s | FileCheck %s --check-prefix=X86-LARGE
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; Make sure fast isel uses rip-relative addressing for the small code model.
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define float @constpool_float(float %x) {
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; CHECK-LABEL: constpool_float:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; CHECK-NEXT: addss %xmm1, %xmm0
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; CHECK-NEXT: retq
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;
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; LARGE-LABEL: constpool_float:
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; LARGE: ## %bb.0:
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; LARGE-NEXT: movabsq $LCPI0_0, %rax
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; LARGE-NEXT: addss (%rax), %xmm0
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; LARGE-NEXT: retq
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;
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; LARGE_PIC-LABEL: constpool_float:
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; LARGE_PIC: # %bb.0:
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; LARGE_PIC-NEXT: .L0$pb:
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; LARGE_PIC-NEXT: leaq .L0$pb(%rip), %rax
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; LARGE_PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.L0$pb, %rcx
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; LARGE_PIC-NEXT: addq %rax, %rcx
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; LARGE_PIC-NEXT: movabsq $.LCPI0_0@GOTOFF, %rax
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; LARGE_PIC-NEXT: addss (%rax,%rcx), %xmm0
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; LARGE_PIC-NEXT: retq
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;
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; AVX-LABEL: constpool_float:
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; AVX: ## %bb.0:
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; AVX-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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; LARGE_AVX-LABEL: constpool_float:
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; LARGE_AVX: ## %bb.0:
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; LARGE_AVX-NEXT: movabsq $LCPI0_0, %rax
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; LARGE_AVX-NEXT: vaddss (%rax), %xmm0, %xmm0
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; LARGE_AVX-NEXT: retq
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;
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; X86-LARGE-LABEL: constpool_float:
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; X86-LARGE: ## %bb.0:
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; X86-LARGE-NEXT: pushl %eax ## encoding: [0x50]
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; X86-LARGE-NEXT: .cfi_def_cfa_offset 8
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; X86-LARGE-NEXT: movss {{[0-9]+}}(%esp), %xmm0 ## encoding: [0xf3,0x0f,0x10,0x44,0x24,0x08]
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; X86-LARGE-NEXT: ## xmm0 = mem[0],zero,zero,zero
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; X86-LARGE-NEXT: addss LCPI0_0, %xmm0 ## encoding: [0xf3,0x0f,0x58,0x05,A,A,A,A]
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; X86-LARGE-NEXT: ## fixup A - offset: 4, value: LCPI0_0, kind: FK_Data_4
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; X86-LARGE-NEXT: movss %xmm0, (%esp) ## encoding: [0xf3,0x0f,0x11,0x04,0x24]
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; X86-LARGE-NEXT: flds (%esp) ## encoding: [0xd9,0x04,0x24]
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; X86-LARGE-NEXT: popl %eax ## encoding: [0x58]
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; X86-LARGE-NEXT: retl ## encoding: [0xc3]
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%1 = fadd float %x, 16.50e+01
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ret float %1
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}
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define double @constpool_double(double %x) nounwind {
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; CHECK-LABEL: constpool_double:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
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; CHECK-NEXT: addsd %xmm1, %xmm0
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; CHECK-NEXT: retq
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;
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; LARGE-LABEL: constpool_double:
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; LARGE: ## %bb.0:
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; LARGE-NEXT: movabsq $LCPI1_0, %rax
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; LARGE-NEXT: addsd (%rax), %xmm0
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; LARGE-NEXT: retq
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;
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; AVX-LABEL: constpool_double:
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; AVX: ## %bb.0:
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; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
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; AVX-NEXT: vaddsd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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; LARGE_AVX-LABEL: constpool_double:
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; LARGE_AVX: ## %bb.0:
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; LARGE_AVX-NEXT: movabsq $LCPI1_0, %rax
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; LARGE_AVX-NEXT: vaddsd (%rax), %xmm0, %xmm0
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; LARGE_AVX-NEXT: retq
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;
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; X86-LARGE-LABEL: constpool_double:
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; X86-LARGE: ## %bb.0:
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; X86-LARGE-NEXT: subl $12, %esp ## encoding: [0x83,0xec,0x0c]
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; X86-LARGE-NEXT: movsd {{[0-9]+}}(%esp), %xmm0 ## encoding: [0xf2,0x0f,0x10,0x44,0x24,0x10]
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; X86-LARGE-NEXT: ## xmm0 = mem[0],zero
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; X86-LARGE-NEXT: addsd LCPI1_0, %xmm0 ## encoding: [0xf2,0x0f,0x58,0x05,A,A,A,A]
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; X86-LARGE-NEXT: ## fixup A - offset: 4, value: LCPI1_0, kind: FK_Data_4
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; X86-LARGE-NEXT: movsd %xmm0, (%esp) ## encoding: [0xf2,0x0f,0x11,0x04,0x24]
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; X86-LARGE-NEXT: fldl (%esp) ## encoding: [0xdd,0x04,0x24]
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; X86-LARGE-NEXT: addl $12, %esp ## encoding: [0x83,0xc4,0x0c]
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; X86-LARGE-NEXT: retl ## encoding: [0xc3]
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%1 = fadd double %x, 8.500000e-01
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ret double %1
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}
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define void @constpool_float_no_fp_args(float* %x) nounwind {
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; CHECK-LABEL: constpool_float_no_fp_args:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; CHECK-NEXT: addss (%rdi), %xmm0
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; CHECK-NEXT: movss %xmm0, (%rdi)
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; CHECK-NEXT: retq
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;
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; LARGE-LABEL: constpool_float_no_fp_args:
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; LARGE: ## %bb.0:
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; LARGE-NEXT: movabsq $LCPI2_0, %rax
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; LARGE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; LARGE-NEXT: addss (%rdi), %xmm0
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; LARGE-NEXT: movss %xmm0, (%rdi)
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; LARGE-NEXT: retq
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;
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; AVX-LABEL: constpool_float_no_fp_args:
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; AVX: ## %bb.0:
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; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; AVX-NEXT: vaddss (%rdi), %xmm0, %xmm0
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; AVX-NEXT: vmovss %xmm0, (%rdi)
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; AVX-NEXT: retq
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;
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; LARGE_AVX-LABEL: constpool_float_no_fp_args:
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; LARGE_AVX: ## %bb.0:
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; LARGE_AVX-NEXT: movabsq $LCPI2_0, %rax
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; LARGE_AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; LARGE_AVX-NEXT: vaddss (%rdi), %xmm0, %xmm0
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; LARGE_AVX-NEXT: vmovss %xmm0, (%rdi)
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; LARGE_AVX-NEXT: retq
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;
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; X86-LARGE-LABEL: constpool_float_no_fp_args:
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; X86-LARGE: ## %bb.0:
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; X86-LARGE-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
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; X86-LARGE-NEXT: movss LCPI2_0, %xmm0 ## encoding: [0xf3,0x0f,0x10,0x05,A,A,A,A]
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; X86-LARGE-NEXT: ## fixup A - offset: 4, value: LCPI2_0, kind: FK_Data_4
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; X86-LARGE-NEXT: ## xmm0 = mem[0],zero,zero,zero
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; X86-LARGE-NEXT: addss (%eax), %xmm0 ## encoding: [0xf3,0x0f,0x58,0x00]
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; X86-LARGE-NEXT: movss %xmm0, (%eax) ## encoding: [0xf3,0x0f,0x11,0x00]
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; X86-LARGE-NEXT: retl ## encoding: [0xc3]
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%a = load float, float* %x
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%b = fadd float %a, 16.50e+01
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store float %b, float* %x
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ret void
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}
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define void @constpool_double_no_fp_args(double* %x) nounwind {
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; CHECK-LABEL: constpool_double_no_fp_args:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; CHECK-NEXT: addsd (%rdi), %xmm0
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; CHECK-NEXT: movsd %xmm0, (%rdi)
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; CHECK-NEXT: retq
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;
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; LARGE-LABEL: constpool_double_no_fp_args:
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; LARGE: ## %bb.0:
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; LARGE-NEXT: movabsq $LCPI3_0, %rax
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; LARGE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; LARGE-NEXT: addsd (%rdi), %xmm0
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; LARGE-NEXT: movsd %xmm0, (%rdi)
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; LARGE-NEXT: retq
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;
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; AVX-LABEL: constpool_double_no_fp_args:
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; AVX: ## %bb.0:
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; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; AVX-NEXT: vaddsd (%rdi), %xmm0, %xmm0
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; AVX-NEXT: vmovsd %xmm0, (%rdi)
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; AVX-NEXT: retq
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;
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; LARGE_AVX-LABEL: constpool_double_no_fp_args:
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; LARGE_AVX: ## %bb.0:
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; LARGE_AVX-NEXT: movabsq $LCPI3_0, %rax
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; LARGE_AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; LARGE_AVX-NEXT: vaddsd (%rdi), %xmm0, %xmm0
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; LARGE_AVX-NEXT: vmovsd %xmm0, (%rdi)
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; LARGE_AVX-NEXT: retq
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;
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; X86-LARGE-LABEL: constpool_double_no_fp_args:
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; X86-LARGE: ## %bb.0:
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; X86-LARGE-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
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; X86-LARGE-NEXT: movsd LCPI3_0, %xmm0 ## encoding: [0xf2,0x0f,0x10,0x05,A,A,A,A]
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; X86-LARGE-NEXT: ## fixup A - offset: 4, value: LCPI3_0, kind: FK_Data_4
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; X86-LARGE-NEXT: ## xmm0 = mem[0],zero
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; X86-LARGE-NEXT: addsd (%eax), %xmm0 ## encoding: [0xf2,0x0f,0x58,0x00]
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; X86-LARGE-NEXT: movsd %xmm0, (%eax) ## encoding: [0xf2,0x0f,0x11,0x00]
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; X86-LARGE-NEXT: retl ## encoding: [0xc3]
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%a = load double, double* %x
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%b = fadd double %a, 8.500000e-01
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store double %b, double* %x
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ret void
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}
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