53 lines
2.3 KiB
LLVM
53 lines
2.3 KiB
LLVM
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; REQUIRES: asserts
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck -check-prefix=X86 %s
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu -debug-only=isel < %s -o /dev/null 2>&1 | FileCheck -check-prefix=DBGDAG %s
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; It's OK to merge the load / store of the first 2 components, but
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; they must not be placed on the same chain after merging.
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; X86-LABEL: {{^}}merge_store_partial_overlap_load:
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; X86-DAG: movzwl ([[BASEREG:%[a-z]+]]), %e[[LO2:[a-z]+]]
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; X86-DAG: movb 2([[BASEREG]]), [[HI1:%[a-z]+]]
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; X86-NEXT: movw %[[LO2]], 1([[BASEREG]])
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; X86-NEXT: movb [[HI1]], 3([[BASEREG]])
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; X86-NEXT: retq
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; DBGDAG-LABEL: Optimized legalized selection DAG: %bb.0 'merge_store_partial_overlap_load:'
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; DBGDAG: [[ENTRYTOKEN:t[0-9]+]]: ch = EntryToken
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; DBGDAG-DAG: [[BASEPTR:t[0-9]+]]: i64,ch = CopyFromReg [[ENTRYTOKEN]],
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; DBGDAG-DAG: [[ADDPTR:t[0-9]+]]: i64 = add {{(nuw )?}}[[BASEPTR]], Constant:i64<2>
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; DBGDAG-DAG: [[LD2:t[0-9]+]]: i16,ch = load<(load 2 from %ir.tmp81, align 1)> [[ENTRYTOKEN]], [[BASEPTR]], undef:i64
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; DBGDAG-DAG: [[LD1:t[0-9]+]]: i8,ch = load<(load 1 from %ir.tmp12)> [[ENTRYTOKEN]], [[ADDPTR]], undef:i64
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; DBGDAG-DAG: [[ST1:t[0-9]+]]: ch = store<(store 1 into %ir.tmp14)> [[ENTRYTOKEN]], [[LD1]], t{{[0-9]+}}, undef:i64
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; DBGDAG-DAG: [[LOADTOKEN:t[0-9]+]]: ch = TokenFactor [[LD2]]:1, [[LD1]]:1
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; DBGDAG-DAG: [[ST2:t[0-9]+]]: ch = store<(store 2 into %ir.tmp10, align 1)> [[LOADTOKEN]], [[LD2]], t{{[0-9]+}}, undef:i64
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; DBGDAG: X86ISD::RET_FLAG t{{[0-9]+}},
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; DBGDAG-LABEL: Instruction selection begins
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define void @merge_store_partial_overlap_load([4 x i8]* %tmp) {
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%tmp8 = getelementptr inbounds [4 x i8], [4 x i8]* %tmp, i32 0, i8 0
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%tmp10 = getelementptr inbounds [4 x i8], [4 x i8]* %tmp, i32 0, i8 1
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%tmp12 = getelementptr inbounds [4 x i8], [4 x i8]* %tmp, i32 0, i8 2
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%tmp14 = getelementptr [4 x i8], [4 x i8]* %tmp, i32 0, i8 3
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%tmp9 = load i8, i8* %tmp8, align 1 ; base + 0
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%tmp11 = load i8, i8* %tmp10, align 1 ; base + 1
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%tmp13 = load i8, i8* %tmp12, align 1 ; base + 2
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store i8 %tmp9, i8* %tmp10, align 1 ; base + 1
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store i8 %tmp11, i8* %tmp12, align 1 ; base + 2
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store i8 %tmp13, i8* %tmp14, align 1 ; base + 3
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; Should emit
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; load base + 0, base + 1
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; store base + 1, base + 2
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; load base + 2
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; store base + 3
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ret void
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}
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