198 lines
6.2 KiB
LLVM
198 lines
6.2 KiB
LLVM
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; RUN: llc < %s -mtriple=i686-pc-win32 -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE2
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; RUN: llc < %s -mtriple=i686-pc-win32 -mattr=+sse2,+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
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; RUN: llc < %s -mtriple=i686-pc-win32 -mattr=+sse2,+avx,+avx512f | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512 --check-prefix=AVX512F
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; RUN: llc < %s -mtriple=i686-pc-win32 -mattr=+sse2,+avx,+avx512vl | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512 --check-prefix=AVX512VL
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; While we don't support varargs with fastcall, we do support forwarding.
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@asdf = internal constant [4 x i8] c"asdf"
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declare void @puts(i8*)
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define i32 @call_fast_thunk() {
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%r = call x86_fastcallcc i32 (...) @fast_thunk(i32 inreg 1, i32 inreg 2, i32 3)
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ret i32 %r
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}
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define x86_fastcallcc i32 @fast_thunk(...) {
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call void @puts(i8* getelementptr ([4 x i8], [4 x i8]* @asdf, i32 0, i32 0))
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%r = musttail call x86_fastcallcc i32 (...) bitcast (i32 (i32, i32, i32)* @fast_target to i32 (...)*) (...)
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ret i32 %r
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}
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; Check that we spill and fill around the call to puts.
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; CHECK-LABEL: @fast_thunk@0:
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; CHECK-DAG: movl %ecx, {{.*}}
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; CHECK-DAG: movl %edx, {{.*}}
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; CHECK: calll _puts
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; CHECK-DAG: movl {{.*}}, %ecx
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; CHECK-DAG: movl {{.*}}, %edx
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; CHECK: jmp @fast_target@12
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define x86_fastcallcc i32 @fast_target(i32 inreg %a, i32 inreg %b, i32 %c) {
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%a0 = add i32 %a, %b
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%a1 = add i32 %a0, %c
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ret i32 %a1
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}
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; Repeat the test for vectorcall, which has XMM registers.
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define i32 @call_vector_thunk() {
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%r = call x86_vectorcallcc i32 (...) @vector_thunk(i32 inreg 1, i32 inreg 2, i32 3)
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ret i32 %r
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}
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define x86_vectorcallcc i32 @vector_thunk(...) {
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call void @puts(i8* getelementptr ([4 x i8], [4 x i8]* @asdf, i32 0, i32 0))
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%r = musttail call x86_vectorcallcc i32 (...) bitcast (i32 (i32, i32, i32)* @vector_target to i32 (...)*) (...)
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ret i32 %r
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}
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; Check that we spill and fill SSE registers around the call to puts.
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; CHECK-LABEL: vector_thunk@@0:
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; CHECK-DAG: movl %ecx, {{.*}}
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; CHECK-DAG: movl %edx, {{.*}}
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; SSE2-DAG: movups %xmm0, {{.*}}
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; SSE2-DAG: movups %xmm1, {{.*}}
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; SSE2-DAG: movups %xmm2, {{.*}}
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; SSE2-DAG: movups %xmm3, {{.*}}
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; SSE2-DAG: movups %xmm4, {{.*}}
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; SSE2-DAG: movups %xmm5, {{.*}}
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; AVX-DAG: vmovups %ymm0, {{.*}}
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; AVX-DAG: vmovups %ymm1, {{.*}}
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; AVX-DAG: vmovups %ymm2, {{.*}}
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; AVX-DAG: vmovups %ymm3, {{.*}}
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; AVX-DAG: vmovups %ymm4, {{.*}}
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; AVX-DAG: vmovups %ymm5, {{.*}}
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; AVX512-DAG: vmovups %zmm0, {{.*}}
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; AVX512-DAG: vmovups %zmm1, {{.*}}
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; AVX512-DAG: vmovups %zmm2, {{.*}}
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; AVX512-DAG: vmovups %zmm3, {{.*}}
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; AVX512-DAG: vmovups %zmm4, {{.*}}
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; AVX512-DAG: vmovups %zmm5, {{.*}}
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; CHECK: calll _puts
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; SSE2-DAG: movups {{.*}}, %xmm0
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; SSE2-DAG: movups {{.*}}, %xmm1
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; SSE2-DAG: movups {{.*}}, %xmm2
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; SSE2-DAG: movups {{.*}}, %xmm3
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; SSE2-DAG: movups {{.*}}, %xmm4
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; SSE2-DAG: movups {{.*}}, %xmm5
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; AVX-DAG: vmovups {{.*}}, %ymm0
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; AVX-DAG: vmovups {{.*}}, %ymm1
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; AVX-DAG: vmovups {{.*}}, %ymm2
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; AVX-DAG: vmovups {{.*}}, %ymm3
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; AVX-DAG: vmovups {{.*}}, %ymm4
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; AVX-DAG: vmovups {{.*}}, %ymm5
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; AVX512-DAG: vmovups {{.*}}, %zmm0
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; AVX512-DAG: vmovups {{.*}}, %zmm1
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; AVX512-DAG: vmovups {{.*}}, %zmm2
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; AVX512-DAG: vmovups {{.*}}, %zmm3
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; AVX512-DAG: vmovups {{.*}}, %zmm4
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; AVX512-DAG: vmovups {{.*}}, %zmm5
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; CHECK-DAG: movl {{.*}}, %ecx
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; CHECK-DAG: movl {{.*}}, %edx
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; CHECK: jmp vector_target@@12
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define x86_vectorcallcc i32 @vector_target(i32 inreg %a, i32 inreg %b, i32 %c) {
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%a0 = add i32 %a, %b
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%a1 = add i32 %a0, %c
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ret i32 %a1
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}
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; Repeat the test for vectorcall, which has XMM registers.
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define i32 @call_vector_thunk_prefer256() "min-legal-vector-width"="256" "prefer-vector-width"="256" {
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%r = call x86_vectorcallcc i32 (...) @vector_thunk_prefer256(i32 inreg 1, i32 inreg 2, i32 3)
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ret i32 %r
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}
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define x86_vectorcallcc i32 @vector_thunk_prefer256(...) "min-legal-vector-width"="256" "prefer-vector-width"="256" {
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call void @puts(i8* getelementptr ([4 x i8], [4 x i8]* @asdf, i32 0, i32 0))
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%r = musttail call x86_vectorcallcc i32 (...) bitcast (i32 (i32, i32, i32)* @vector_target_prefer256 to i32 (...)*) (...)
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ret i32 %r
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}
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; Check that we spill and fill SSE registers around the call to puts.
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; CHECK-LABEL: vector_thunk_prefer256@@0:
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; CHECK-DAG: movl %ecx, {{.*}}
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; CHECK-DAG: movl %edx, {{.*}}
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; SSE2-DAG: movups %xmm0, {{.*}}
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; SSE2-DAG: movups %xmm1, {{.*}}
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; SSE2-DAG: movups %xmm2, {{.*}}
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; SSE2-DAG: movups %xmm3, {{.*}}
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; SSE2-DAG: movups %xmm4, {{.*}}
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; SSE2-DAG: movups %xmm5, {{.*}}
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; AVX-DAG: vmovups %ymm0, {{.*}}
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; AVX-DAG: vmovups %ymm1, {{.*}}
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; AVX-DAG: vmovups %ymm2, {{.*}}
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; AVX-DAG: vmovups %ymm3, {{.*}}
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; AVX-DAG: vmovups %ymm4, {{.*}}
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; AVX-DAG: vmovups %ymm5, {{.*}}
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; AVX512F-DAG: vmovups %zmm0, {{.*}}
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; AVX512F-DAG: vmovups %zmm1, {{.*}}
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; AVX512F-DAG: vmovups %zmm2, {{.*}}
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; AVX512F-DAG: vmovups %zmm3, {{.*}}
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; AVX512F-DAG: vmovups %zmm4, {{.*}}
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; AVX512F-DAG: vmovups %zmm5, {{.*}}
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; AVX512VL-DAG: vmovups %ymm0, {{.*}}
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; AVX512VL-DAG: vmovups %ymm1, {{.*}}
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; AVX512VL-DAG: vmovups %ymm2, {{.*}}
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; AVX512VL-DAG: vmovups %ymm3, {{.*}}
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; AVX512VL-DAG: vmovups %ymm4, {{.*}}
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; AVX512VL-DAG: vmovups %ymm5, {{.*}}
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; CHECK: calll _puts
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; SSE2-DAG: movups {{.*}}, %xmm0
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; SSE2-DAG: movups {{.*}}, %xmm1
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; SSE2-DAG: movups {{.*}}, %xmm2
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; SSE2-DAG: movups {{.*}}, %xmm3
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; SSE2-DAG: movups {{.*}}, %xmm4
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; SSE2-DAG: movups {{.*}}, %xmm5
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; AVX-DAG: vmovups {{.*}}, %ymm0
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; AVX-DAG: vmovups {{.*}}, %ymm1
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; AVX-DAG: vmovups {{.*}}, %ymm2
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; AVX-DAG: vmovups {{.*}}, %ymm3
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; AVX-DAG: vmovups {{.*}}, %ymm4
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; AVX-DAG: vmovups {{.*}}, %ymm5
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; AVX512F-DAG: vmovups {{.*}}, %zmm0
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; AVX512F-DAG: vmovups {{.*}}, %zmm1
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; AVX512F-DAG: vmovups {{.*}}, %zmm2
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; AVX512F-DAG: vmovups {{.*}}, %zmm3
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; AVX512F-DAG: vmovups {{.*}}, %zmm4
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; AVX512F-DAG: vmovups {{.*}}, %zmm5
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; AVX512VL-DAG: vmovups {{.*}}, %ymm0
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; AVX512VL-DAG: vmovups {{.*}}, %ymm1
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; AVX512VL-DAG: vmovups {{.*}}, %ymm2
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; AVX512VL-DAG: vmovups {{.*}}, %ymm3
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; AVX512VL-DAG: vmovups {{.*}}, %ymm4
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; AVX512VL-DAG: vmovups {{.*}}, %ymm5
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; CHECK-DAG: movl {{.*}}, %ecx
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; CHECK-DAG: movl {{.*}}, %edx
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; CHECK: jmp vector_target_prefer256@@12
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define x86_vectorcallcc i32 @vector_target_prefer256(i32 inreg %a, i32 inreg %b, i32 %c) "min-legal-vector-width"="256" "prefer-vector-width"="256" {
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%a0 = add i32 %a, %b
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%a1 = add i32 %a0, %c
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ret i32 %a1
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}
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