378 lines
11 KiB
LLVM
378 lines
11 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=i386-linux-gnu -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK32
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; RUN: llc -mtriple=x86_64-linux-gnu -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK64
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; The peephole optimizer can elide some physical register copies such as
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; EFLAGS. Make sure the flags are used directly, instead of needlessly using
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; saving and restoring specific conditions.
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@L = external dso_local global i32
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@M = external dso_local global i8
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declare i32 @bar(i64)
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define i1 @plus_one() nounwind {
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; CHECK32-LABEL: plus_one:
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; CHECK32: # %bb.0: # %entry
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; CHECK32-NEXT: movb M, %al
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; CHECK32-NEXT: incl L
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; CHECK32-NEXT: jne .LBB0_2
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; CHECK32-NEXT: # %bb.1: # %entry
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; CHECK32-NEXT: andb $8, %al
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; CHECK32-NEXT: je .LBB0_2
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; CHECK32-NEXT: # %bb.3: # %exit2
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; CHECK32-NEXT: xorl %eax, %eax
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; CHECK32-NEXT: retl
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; CHECK32-NEXT: .LBB0_2: # %exit
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; CHECK32-NEXT: movb $1, %al
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; CHECK32-NEXT: retl
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;
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; CHECK64-LABEL: plus_one:
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; CHECK64: # %bb.0: # %entry
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; CHECK64-NEXT: movb {{.*}}(%rip), %al
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; CHECK64-NEXT: incl {{.*}}(%rip)
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; CHECK64-NEXT: jne .LBB0_2
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; CHECK64-NEXT: # %bb.1: # %entry
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; CHECK64-NEXT: andb $8, %al
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; CHECK64-NEXT: je .LBB0_2
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; CHECK64-NEXT: # %bb.3: # %exit2
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; CHECK64-NEXT: xorl %eax, %eax
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; CHECK64-NEXT: retq
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; CHECK64-NEXT: .LBB0_2: # %exit
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; CHECK64-NEXT: movb $1, %al
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; CHECK64-NEXT: retq
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entry:
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%loaded_L = load i32, i32* @L
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%val = add nsw i32 %loaded_L, 1 ; N.B. will emit inc.
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store i32 %val, i32* @L
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%loaded_M = load i8, i8* @M
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%masked = and i8 %loaded_M, 8
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%M_is_true = icmp ne i8 %masked, 0
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%L_is_false = icmp eq i32 %val, 0
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%cond = and i1 %L_is_false, %M_is_true
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br i1 %cond, label %exit2, label %exit
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exit:
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ret i1 true
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exit2:
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ret i1 false
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}
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define i1 @plus_forty_two() nounwind {
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; CHECK32-LABEL: plus_forty_two:
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; CHECK32: # %bb.0: # %entry
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; CHECK32-NEXT: movb M, %al
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; CHECK32-NEXT: addl $42, L
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; CHECK32-NEXT: jne .LBB1_2
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; CHECK32-NEXT: # %bb.1: # %entry
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; CHECK32-NEXT: andb $8, %al
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; CHECK32-NEXT: je .LBB1_2
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; CHECK32-NEXT: # %bb.3: # %exit2
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; CHECK32-NEXT: xorl %eax, %eax
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; CHECK32-NEXT: retl
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; CHECK32-NEXT: .LBB1_2: # %exit
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; CHECK32-NEXT: movb $1, %al
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; CHECK32-NEXT: retl
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;
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; CHECK64-LABEL: plus_forty_two:
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; CHECK64: # %bb.0: # %entry
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; CHECK64-NEXT: movb {{.*}}(%rip), %al
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; CHECK64-NEXT: addl $42, {{.*}}(%rip)
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; CHECK64-NEXT: jne .LBB1_2
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; CHECK64-NEXT: # %bb.1: # %entry
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; CHECK64-NEXT: andb $8, %al
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; CHECK64-NEXT: je .LBB1_2
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; CHECK64-NEXT: # %bb.3: # %exit2
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; CHECK64-NEXT: xorl %eax, %eax
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; CHECK64-NEXT: retq
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; CHECK64-NEXT: .LBB1_2: # %exit
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; CHECK64-NEXT: movb $1, %al
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; CHECK64-NEXT: retq
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entry:
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%loaded_L = load i32, i32* @L
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%val = add nsw i32 %loaded_L, 42 ; N.B. won't emit inc.
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store i32 %val, i32* @L
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%loaded_M = load i8, i8* @M
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%masked = and i8 %loaded_M, 8
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%M_is_true = icmp ne i8 %masked, 0
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%L_is_false = icmp eq i32 %val, 0
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%cond = and i1 %L_is_false, %M_is_true
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br i1 %cond, label %exit2, label %exit
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exit:
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ret i1 true
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exit2:
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ret i1 false
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}
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define i1 @minus_one() nounwind {
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; CHECK32-LABEL: minus_one:
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; CHECK32: # %bb.0: # %entry
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; CHECK32-NEXT: movb M, %al
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; CHECK32-NEXT: decl L
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; CHECK32-NEXT: jne .LBB2_2
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; CHECK32-NEXT: # %bb.1: # %entry
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; CHECK32-NEXT: andb $8, %al
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; CHECK32-NEXT: je .LBB2_2
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; CHECK32-NEXT: # %bb.3: # %exit2
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; CHECK32-NEXT: xorl %eax, %eax
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; CHECK32-NEXT: retl
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; CHECK32-NEXT: .LBB2_2: # %exit
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; CHECK32-NEXT: movb $1, %al
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; CHECK32-NEXT: retl
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;
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; CHECK64-LABEL: minus_one:
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; CHECK64: # %bb.0: # %entry
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; CHECK64-NEXT: movb {{.*}}(%rip), %al
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; CHECK64-NEXT: decl {{.*}}(%rip)
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; CHECK64-NEXT: jne .LBB2_2
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; CHECK64-NEXT: # %bb.1: # %entry
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; CHECK64-NEXT: andb $8, %al
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; CHECK64-NEXT: je .LBB2_2
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; CHECK64-NEXT: # %bb.3: # %exit2
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; CHECK64-NEXT: xorl %eax, %eax
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; CHECK64-NEXT: retq
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; CHECK64-NEXT: .LBB2_2: # %exit
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; CHECK64-NEXT: movb $1, %al
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; CHECK64-NEXT: retq
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entry:
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%loaded_L = load i32, i32* @L
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%val = add nsw i32 %loaded_L, -1 ; N.B. will emit dec.
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store i32 %val, i32* @L
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%loaded_M = load i8, i8* @M
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%masked = and i8 %loaded_M, 8
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%M_is_true = icmp ne i8 %masked, 0
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%L_is_false = icmp eq i32 %val, 0
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%cond = and i1 %L_is_false, %M_is_true
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br i1 %cond, label %exit2, label %exit
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exit:
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ret i1 true
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exit2:
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ret i1 false
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}
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define i1 @minus_forty_two() nounwind {
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; CHECK32-LABEL: minus_forty_two:
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; CHECK32: # %bb.0: # %entry
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; CHECK32-NEXT: movb M, %al
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; CHECK32-NEXT: addl $-42, L
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; CHECK32-NEXT: jne .LBB3_2
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; CHECK32-NEXT: # %bb.1: # %entry
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; CHECK32-NEXT: andb $8, %al
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; CHECK32-NEXT: je .LBB3_2
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; CHECK32-NEXT: # %bb.3: # %exit2
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; CHECK32-NEXT: xorl %eax, %eax
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; CHECK32-NEXT: retl
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; CHECK32-NEXT: .LBB3_2: # %exit
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; CHECK32-NEXT: movb $1, %al
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; CHECK32-NEXT: retl
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;
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; CHECK64-LABEL: minus_forty_two:
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; CHECK64: # %bb.0: # %entry
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; CHECK64-NEXT: movb {{.*}}(%rip), %al
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; CHECK64-NEXT: addl $-42, {{.*}}(%rip)
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; CHECK64-NEXT: jne .LBB3_2
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; CHECK64-NEXT: # %bb.1: # %entry
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; CHECK64-NEXT: andb $8, %al
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; CHECK64-NEXT: je .LBB3_2
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; CHECK64-NEXT: # %bb.3: # %exit2
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; CHECK64-NEXT: xorl %eax, %eax
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; CHECK64-NEXT: retq
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; CHECK64-NEXT: .LBB3_2: # %exit
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; CHECK64-NEXT: movb $1, %al
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; CHECK64-NEXT: retq
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entry:
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%loaded_L = load i32, i32* @L
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%val = add nsw i32 %loaded_L, -42 ; N.B. won't emit dec.
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store i32 %val, i32* @L
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%loaded_M = load i8, i8* @M
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%masked = and i8 %loaded_M, 8
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%M_is_true = icmp ne i8 %masked, 0
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%L_is_false = icmp eq i32 %val, 0
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%cond = and i1 %L_is_false, %M_is_true
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br i1 %cond, label %exit2, label %exit
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exit:
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ret i1 true
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exit2:
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ret i1 false
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}
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define i64 @test_intervening_call(i64* %foo, i64 %bar, i64 %baz) nounwind {
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; CHECK32-LABEL: test_intervening_call:
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; CHECK32: # %bb.0: # %entry
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; CHECK32-NEXT: pushl %ebx
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; CHECK32-NEXT: pushl %esi
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; CHECK32-NEXT: pushl %eax
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ebx
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
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; CHECK32-NEXT: lock cmpxchg8b (%esi)
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; CHECK32-NEXT: setne %bl
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; CHECK32-NEXT: subl $8, %esp
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; CHECK32-NEXT: pushl %edx
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; CHECK32-NEXT: pushl %eax
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; CHECK32-NEXT: calll bar
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; CHECK32-NEXT: addl $16, %esp
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; CHECK32-NEXT: testb %bl, %bl
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; CHECK32-NEXT: jne .LBB4_3
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; CHECK32-NEXT: # %bb.1: # %t
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; CHECK32-NEXT: movl $42, %eax
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; CHECK32-NEXT: jmp .LBB4_2
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; CHECK32-NEXT: .LBB4_3: # %f
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; CHECK32-NEXT: xorl %eax, %eax
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; CHECK32-NEXT: .LBB4_2: # %t
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; CHECK32-NEXT: xorl %edx, %edx
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; CHECK32-NEXT: addl $4, %esp
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; CHECK32-NEXT: popl %esi
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; CHECK32-NEXT: popl %ebx
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; CHECK32-NEXT: retl
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;
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; CHECK64-LABEL: test_intervening_call:
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; CHECK64: # %bb.0: # %entry
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; CHECK64-NEXT: pushq %rbx
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; CHECK64-NEXT: movq %rsi, %rax
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; CHECK64-NEXT: lock cmpxchgq %rdx, (%rdi)
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; CHECK64-NEXT: setne %bl
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; CHECK64-NEXT: movq %rax, %rdi
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; CHECK64-NEXT: callq bar
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; CHECK64-NEXT: testb %bl, %bl
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; CHECK64-NEXT: jne .LBB4_2
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; CHECK64-NEXT: # %bb.1: # %t
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; CHECK64-NEXT: movl $42, %eax
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; CHECK64-NEXT: popq %rbx
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; CHECK64-NEXT: retq
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; CHECK64-NEXT: .LBB4_2: # %f
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; CHECK64-NEXT: xorl %eax, %eax
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; CHECK64-NEXT: popq %rbx
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; CHECK64-NEXT: retq
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entry:
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; cmpxchg sets EFLAGS, call clobbers it, then br uses EFLAGS.
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%cx = cmpxchg i64* %foo, i64 %bar, i64 %baz seq_cst seq_cst
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%v = extractvalue { i64, i1 } %cx, 0
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%p = extractvalue { i64, i1 } %cx, 1
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call i32 @bar(i64 %v)
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br i1 %p, label %t, label %f
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t:
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ret i64 42
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f:
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ret i64 0
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}
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define i64 @test_two_live_flags(i64* %foo0, i64 %bar0, i64 %baz0, i64* %foo1, i64 %bar1, i64 %baz1) nounwind {
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; CHECK32-LABEL: test_two_live_flags:
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; CHECK32: # %bb.0: # %entry
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; CHECK32-NEXT: pushl %ebp
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; CHECK32-NEXT: pushl %ebx
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; CHECK32-NEXT: pushl %edi
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; CHECK32-NEXT: pushl %esi
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; CHECK32-NEXT: pushl %eax
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edi
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ebp
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ebx
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
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; CHECK32-NEXT: lock cmpxchg8b (%esi)
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; CHECK32-NEXT: setne {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK32-NEXT: movl %edi, %edx
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; CHECK32-NEXT: movl %ebp, %ecx
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ebx
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; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
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; CHECK32-NEXT: lock cmpxchg8b (%esi)
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; CHECK32-NEXT: sete %al
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; CHECK32-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload
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; CHECK32-NEXT: jne .LBB5_4
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; CHECK32-NEXT: # %bb.1: # %entry
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; CHECK32-NEXT: testb %al, %al
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; CHECK32-NEXT: je .LBB5_4
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; CHECK32-NEXT: # %bb.2: # %t
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; CHECK32-NEXT: movl $42, %eax
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; CHECK32-NEXT: jmp .LBB5_3
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; CHECK32-NEXT: .LBB5_4: # %f
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; CHECK32-NEXT: xorl %eax, %eax
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; CHECK32-NEXT: .LBB5_3: # %t
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; CHECK32-NEXT: xorl %edx, %edx
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; CHECK32-NEXT: addl $4, %esp
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; CHECK32-NEXT: popl %esi
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; CHECK32-NEXT: popl %edi
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; CHECK32-NEXT: popl %ebx
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; CHECK32-NEXT: popl %ebp
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; CHECK32-NEXT: retl
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;
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|
|
; CHECK64-LABEL: test_two_live_flags:
|
||
|
|
; CHECK64: # %bb.0: # %entry
|
||
|
|
; CHECK64-NEXT: movq %rsi, %rax
|
||
|
|
; CHECK64-NEXT: lock cmpxchgq %rdx, (%rdi)
|
||
|
|
; CHECK64-NEXT: setne %dl
|
||
|
|
; CHECK64-NEXT: movq %r8, %rax
|
||
|
|
; CHECK64-NEXT: lock cmpxchgq %r9, (%rcx)
|
||
|
|
; CHECK64-NEXT: sete %al
|
||
|
|
; CHECK64-NEXT: testb %dl, %dl
|
||
|
|
; CHECK64-NEXT: jne .LBB5_3
|
||
|
|
; CHECK64-NEXT: # %bb.1: # %entry
|
||
|
|
; CHECK64-NEXT: testb %al, %al
|
||
|
|
; CHECK64-NEXT: je .LBB5_3
|
||
|
|
; CHECK64-NEXT: # %bb.2: # %t
|
||
|
|
; CHECK64-NEXT: movl $42, %eax
|
||
|
|
; CHECK64-NEXT: retq
|
||
|
|
; CHECK64-NEXT: .LBB5_3: # %f
|
||
|
|
; CHECK64-NEXT: xorl %eax, %eax
|
||
|
|
; CHECK64-NEXT: retq
|
||
|
|
entry:
|
||
|
|
%cx0 = cmpxchg i64* %foo0, i64 %bar0, i64 %baz0 seq_cst seq_cst
|
||
|
|
%p0 = extractvalue { i64, i1 } %cx0, 1
|
||
|
|
%cx1 = cmpxchg i64* %foo1, i64 %bar1, i64 %baz1 seq_cst seq_cst
|
||
|
|
%p1 = extractvalue { i64, i1 } %cx1, 1
|
||
|
|
%flag = and i1 %p0, %p1
|
||
|
|
br i1 %flag, label %t, label %f
|
||
|
|
|
||
|
|
t:
|
||
|
|
ret i64 42
|
||
|
|
|
||
|
|
f:
|
||
|
|
ret i64 0
|
||
|
|
}
|
||
|
|
|
||
|
|
define i1 @asm_clobbering_flags(i32* %mem) nounwind {
|
||
|
|
; CHECK32-LABEL: asm_clobbering_flags:
|
||
|
|
; CHECK32: # %bb.0: # %entry
|
||
|
|
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||
|
|
; CHECK32-NEXT: movl (%ecx), %edx
|
||
|
|
; CHECK32-NEXT: testl %edx, %edx
|
||
|
|
; CHECK32-NEXT: setg %al
|
||
|
|
; CHECK32-NEXT: #APP
|
||
|
|
; CHECK32-NEXT: bsfl %edx, %edx
|
||
|
|
; CHECK32-NEXT: #NO_APP
|
||
|
|
; CHECK32-NEXT: movl %edx, (%ecx)
|
||
|
|
; CHECK32-NEXT: retl
|
||
|
|
;
|
||
|
|
; CHECK64-LABEL: asm_clobbering_flags:
|
||
|
|
; CHECK64: # %bb.0: # %entry
|
||
|
|
; CHECK64-NEXT: movl (%rdi), %ecx
|
||
|
|
; CHECK64-NEXT: testl %ecx, %ecx
|
||
|
|
; CHECK64-NEXT: setg %al
|
||
|
|
; CHECK64-NEXT: #APP
|
||
|
|
; CHECK64-NEXT: bsfl %ecx, %ecx
|
||
|
|
; CHECK64-NEXT: #NO_APP
|
||
|
|
; CHECK64-NEXT: movl %ecx, (%rdi)
|
||
|
|
; CHECK64-NEXT: retq
|
||
|
|
entry:
|
||
|
|
%val = load i32, i32* %mem, align 4
|
||
|
|
%cmp = icmp sgt i32 %val, 0
|
||
|
|
%res = tail call i32 asm "bsfl $1,$0", "=r,r,~{cc},~{dirflag},~{fpsr},~{flags}"(i32 %val)
|
||
|
|
store i32 %res, i32* %mem, align 4
|
||
|
|
ret i1 %cmp
|
||
|
|
}
|