359 lines
14 KiB
LLVM
359 lines
14 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+adx < %s | FileCheck %s --check-prefix=CHECK
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; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=-adx < %s | FileCheck %s --check-prefix=CHECK
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-unknown"
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; Stack reload folding tests.
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;
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; By including a nop call with sideeffects we can force a partial register spill of the
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; relevant registers and check that the reload is correctly folded into the instruction.
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define i8 @stack_fold_addcarry_u32(i8 %a0, i32 %a1, i32 %a2, i8* %a3) {
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; CHECK-LABEL: stack_fold_addcarry_u32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: pushq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: pushq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: pushq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: pushq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 56
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; CHECK-NEXT: .cfi_offset %rbx, -56
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; CHECK-NEXT: .cfi_offset %r12, -48
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; CHECK-NEXT: .cfi_offset %r13, -40
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; CHECK-NEXT: .cfi_offset %r14, -32
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; CHECK-NEXT: .cfi_offset %r15, -24
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; CHECK-NEXT: .cfi_offset %rbp, -16
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; CHECK-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
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; CHECK-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
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; CHECK-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
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; CHECK-NEXT: #APP
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; CHECK-NEXT: nop
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
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; CHECK-NEXT: addb $-1, %al
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; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload
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; CHECK-NEXT: adcl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Folded Reload
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; CHECK-NEXT: setb %al
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; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
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; CHECK-NEXT: movl %edx, (%rcx)
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: popq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: popq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: popq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: popq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
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%2 = call { i8, i32 } @llvm.x86.addcarry.32(i8 %a0, i32 %a1, i32 %a2)
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%3 = extractvalue { i8, i32 } %2, 1
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%4 = bitcast i8* %a3 to i32*
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store i32 %3, i32* %4, align 1
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%5 = extractvalue { i8, i32 } %2, 0
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ret i8 %5
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}
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define i8 @stack_fold_addcarry_u64(i8 %a0, i64 %a1, i64 %a2, i8* %a3) {
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; CHECK-LABEL: stack_fold_addcarry_u64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: pushq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: pushq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: pushq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: pushq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 56
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; CHECK-NEXT: .cfi_offset %rbx, -56
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; CHECK-NEXT: .cfi_offset %r12, -48
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; CHECK-NEXT: .cfi_offset %r13, -40
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; CHECK-NEXT: .cfi_offset %r14, -32
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; CHECK-NEXT: .cfi_offset %r15, -24
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; CHECK-NEXT: .cfi_offset %rbp, -16
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; CHECK-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
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; CHECK-NEXT: #APP
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; CHECK-NEXT: nop
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
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; CHECK-NEXT: addb $-1, %al
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; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
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; CHECK-NEXT: adcq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Folded Reload
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; CHECK-NEXT: setb %al
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; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
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; CHECK-NEXT: movq %rdx, (%rcx)
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: popq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: popq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: popq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: popq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
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%2 = call { i8, i64 } @llvm.x86.addcarry.64(i8 %a0, i64 %a1, i64 %a2)
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%3 = extractvalue { i8, i64 } %2, 1
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%4 = bitcast i8* %a3 to i64*
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store i64 %3, i64* %4, align 1
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%5 = extractvalue { i8, i64 } %2, 0
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ret i8 %5
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}
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define i8 @stack_fold_addcarryx_u32(i8 %a0, i32 %a1, i32 %a2, i8* %a3) {
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; CHECK-LABEL: stack_fold_addcarryx_u32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: pushq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: pushq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: pushq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: pushq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 56
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; CHECK-NEXT: .cfi_offset %rbx, -56
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; CHECK-NEXT: .cfi_offset %r12, -48
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; CHECK-NEXT: .cfi_offset %r13, -40
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; CHECK-NEXT: .cfi_offset %r14, -32
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; CHECK-NEXT: .cfi_offset %r15, -24
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; CHECK-NEXT: .cfi_offset %rbp, -16
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; CHECK-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
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; CHECK-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
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; CHECK-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
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; CHECK-NEXT: #APP
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; CHECK-NEXT: nop
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
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; CHECK-NEXT: addb $-1, %al
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; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload
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; CHECK-NEXT: adcl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Folded Reload
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; CHECK-NEXT: setb %al
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; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
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; CHECK-NEXT: movl %edx, (%rcx)
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: popq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: popq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: popq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: popq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
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%2 = call { i8, i32 } @llvm.x86.addcarry.32(i8 %a0, i32 %a1, i32 %a2)
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%3 = extractvalue { i8, i32 } %2, 1
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%4 = bitcast i8* %a3 to i32*
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store i32 %3, i32* %4, align 1
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%5 = extractvalue { i8, i32 } %2, 0
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ret i8 %5
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}
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define i8 @stack_fold_addcarryx_u64(i8 %a0, i64 %a1, i64 %a2, i8* %a3) {
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; CHECK-LABEL: stack_fold_addcarryx_u64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: pushq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: pushq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: pushq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: pushq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 56
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; CHECK-NEXT: .cfi_offset %rbx, -56
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; CHECK-NEXT: .cfi_offset %r12, -48
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; CHECK-NEXT: .cfi_offset %r13, -40
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; CHECK-NEXT: .cfi_offset %r14, -32
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; CHECK-NEXT: .cfi_offset %r15, -24
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; CHECK-NEXT: .cfi_offset %rbp, -16
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; CHECK-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
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; CHECK-NEXT: #APP
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; CHECK-NEXT: nop
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
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; CHECK-NEXT: addb $-1, %al
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; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
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; CHECK-NEXT: adcq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Folded Reload
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; CHECK-NEXT: setb %al
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; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
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; CHECK-NEXT: movq %rdx, (%rcx)
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: popq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: popq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: popq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: popq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
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%2 = call { i8, i64 } @llvm.x86.addcarry.64(i8 %a0, i64 %a1, i64 %a2)
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%3 = extractvalue { i8, i64 } %2, 1
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%4 = bitcast i8* %a3 to i64*
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store i64 %3, i64* %4, align 1
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%5 = extractvalue { i8, i64 } %2, 0
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ret i8 %5
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}
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define i8 @stack_fold_subborrow_u32(i8 %a0, i32 %a1, i32 %a2, i8* %a3) {
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; CHECK-LABEL: stack_fold_subborrow_u32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: pushq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: pushq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: pushq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: pushq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 56
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; CHECK-NEXT: .cfi_offset %rbx, -56
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; CHECK-NEXT: .cfi_offset %r12, -48
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; CHECK-NEXT: .cfi_offset %r13, -40
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; CHECK-NEXT: .cfi_offset %r14, -32
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; CHECK-NEXT: .cfi_offset %r15, -24
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; CHECK-NEXT: .cfi_offset %rbp, -16
|
||
|
|
; CHECK-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
|
||
|
|
; CHECK-NEXT: movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
|
||
|
|
; CHECK-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
|
||
|
|
; CHECK-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
|
||
|
|
; CHECK-NEXT: #APP
|
||
|
|
; CHECK-NEXT: nop
|
||
|
|
; CHECK-NEXT: #NO_APP
|
||
|
|
; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
|
||
|
|
; CHECK-NEXT: addb $-1, %al
|
||
|
|
; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload
|
||
|
|
; CHECK-NEXT: sbbl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Folded Reload
|
||
|
|
; CHECK-NEXT: setb %al
|
||
|
|
; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
|
||
|
|
; CHECK-NEXT: movl %edx, (%rcx)
|
||
|
|
; CHECK-NEXT: popq %rbx
|
||
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 48
|
||
|
|
; CHECK-NEXT: popq %r12
|
||
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 40
|
||
|
|
; CHECK-NEXT: popq %r13
|
||
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 32
|
||
|
|
; CHECK-NEXT: popq %r14
|
||
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 24
|
||
|
|
; CHECK-NEXT: popq %r15
|
||
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 16
|
||
|
|
; CHECK-NEXT: popq %rbp
|
||
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 8
|
||
|
|
; CHECK-NEXT: retq
|
||
|
|
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
|
||
|
|
%2 = call { i8, i32 } @llvm.x86.subborrow.32(i8 %a0, i32 %a1, i32 %a2)
|
||
|
|
%3 = extractvalue { i8, i32 } %2, 1
|
||
|
|
%4 = bitcast i8* %a3 to i32*
|
||
|
|
store i32 %3, i32* %4, align 1
|
||
|
|
%5 = extractvalue { i8, i32 } %2, 0
|
||
|
|
ret i8 %5
|
||
|
|
}
|
||
|
|
|
||
|
|
define i8 @stack_fold_subborrow_u64(i8 %a0, i64 %a1, i64 %a2, i8* %a3) {
|
||
|
|
; CHECK-LABEL: stack_fold_subborrow_u64:
|
||
|
|
; CHECK: # %bb.0:
|
||
|
|
; CHECK-NEXT: pushq %rbp
|
||
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 16
|
||
|
|
; CHECK-NEXT: pushq %r15
|
||
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 24
|
||
|
|
; CHECK-NEXT: pushq %r14
|
||
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 32
|
||
|
|
; CHECK-NEXT: pushq %r13
|
||
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 40
|
||
|
|
; CHECK-NEXT: pushq %r12
|
||
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 48
|
||
|
|
; CHECK-NEXT: pushq %rbx
|
||
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 56
|
||
|
|
; CHECK-NEXT: .cfi_offset %rbx, -56
|
||
|
|
; CHECK-NEXT: .cfi_offset %r12, -48
|
||
|
|
; CHECK-NEXT: .cfi_offset %r13, -40
|
||
|
|
; CHECK-NEXT: .cfi_offset %r14, -32
|
||
|
|
; CHECK-NEXT: .cfi_offset %r15, -24
|
||
|
|
; CHECK-NEXT: .cfi_offset %rbp, -16
|
||
|
|
; CHECK-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
|
||
|
|
; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
|
||
|
|
; CHECK-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
|
||
|
|
; CHECK-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
|
||
|
|
; CHECK-NEXT: #APP
|
||
|
|
; CHECK-NEXT: nop
|
||
|
|
; CHECK-NEXT: #NO_APP
|
||
|
|
; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
|
||
|
|
; CHECK-NEXT: addb $-1, %al
|
||
|
|
; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
|
||
|
|
; CHECK-NEXT: sbbq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Folded Reload
|
||
|
|
; CHECK-NEXT: setb %al
|
||
|
|
; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
|
||
|
|
; CHECK-NEXT: movq %rdx, (%rcx)
|
||
|
|
; CHECK-NEXT: popq %rbx
|
||
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 48
|
||
|
|
; CHECK-NEXT: popq %r12
|
||
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 40
|
||
|
|
; CHECK-NEXT: popq %r13
|
||
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 32
|
||
|
|
; CHECK-NEXT: popq %r14
|
||
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 24
|
||
|
|
; CHECK-NEXT: popq %r15
|
||
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 16
|
||
|
|
; CHECK-NEXT: popq %rbp
|
||
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 8
|
||
|
|
; CHECK-NEXT: retq
|
||
|
|
%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
|
||
|
|
%2 = call { i8, i64 } @llvm.x86.subborrow.64(i8 %a0, i64 %a1, i64 %a2)
|
||
|
|
%3 = extractvalue { i8, i64 } %2, 1
|
||
|
|
%4 = bitcast i8* %a3 to i64*
|
||
|
|
store i64 %3, i64* %4, align 1
|
||
|
|
%5 = extractvalue { i8, i64 } %2, 0
|
||
|
|
ret i8 %5
|
||
|
|
}
|
||
|
|
|
||
|
|
declare { i8, i32 } @llvm.x86.addcarry.32(i8, i32, i32)
|
||
|
|
declare { i8, i64 } @llvm.x86.addcarry.64(i8, i64, i64)
|
||
|
|
declare { i8, i32 } @llvm.x86.subborrow.32(i8, i32, i32)
|
||
|
|
declare { i8, i64 } @llvm.x86.subborrow.64(i8, i64, i64)
|