91 lines
3.3 KiB
LLVM
91 lines
3.3 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=SSE --check-prefix=SSSE3
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
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define <4 x i32> @load_zmov_4i32_to_0zzz(<4 x i32> *%ptr) {
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; SSE-LABEL: load_zmov_4i32_to_0zzz:
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; SSE: # %bb.0: # %entry
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; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: load_zmov_4i32_to_0zzz:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; AVX-NEXT: retq
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entry:
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%X = load <4 x i32>, <4 x i32>* %ptr
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%Y = shufflevector <4 x i32> %X, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 4, i32 4>
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ret <4 x i32>%Y
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}
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define <2 x i64> @load_zmov_2i64_to_0z(<2 x i64> *%ptr) {
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; SSE-LABEL: load_zmov_2i64_to_0z:
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; SSE: # %bb.0: # %entry
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; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: load_zmov_2i64_to_0z:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; AVX-NEXT: retq
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entry:
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%X = load <2 x i64>, <2 x i64>* %ptr
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%Y = shufflevector <2 x i64> %X, <2 x i64> zeroinitializer, <2 x i32> <i32 0, i32 2>
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ret <2 x i64>%Y
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}
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define <4 x i32> @load_zmov_4i32_to_0zzz_volatile(<4 x i32> *%ptr) {
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; SSE2-LABEL: load_zmov_4i32_to_0zzz_volatile:
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; SSE2: # %bb.0: # %entry
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; SSE2-NEXT: movaps (%rdi), %xmm1
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; SSE2-NEXT: xorps %xmm0, %xmm0
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; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: load_zmov_4i32_to_0zzz_volatile:
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; SSSE3: # %bb.0: # %entry
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; SSSE3-NEXT: movaps (%rdi), %xmm1
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; SSSE3-NEXT: xorps %xmm0, %xmm0
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; SSSE3-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: load_zmov_4i32_to_0zzz_volatile:
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; SSE41: # %bb.0: # %entry
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; SSE41-NEXT: movaps (%rdi), %xmm1
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; SSE41-NEXT: xorps %xmm0, %xmm0
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: load_zmov_4i32_to_0zzz_volatile:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vmovaps (%rdi), %xmm0
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; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
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; AVX-NEXT: retq
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entry:
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%X = load volatile <4 x i32>, <4 x i32>* %ptr
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%Y = shufflevector <4 x i32> %X, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 4, i32 4>
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ret <4 x i32>%Y
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}
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define <2 x i64> @load_zmov_2i64_to_0z_volatile(<2 x i64> *%ptr) {
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; SSE-LABEL: load_zmov_2i64_to_0z_volatile:
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; SSE: # %bb.0: # %entry
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; SSE-NEXT: movdqa (%rdi), %xmm0
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; SSE-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: load_zmov_2i64_to_0z_volatile:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vmovdqa (%rdi), %xmm0
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; AVX-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
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; AVX-NEXT: retq
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entry:
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%X = load volatile <2 x i64>, <2 x i64>* %ptr
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%Y = shufflevector <2 x i64> %X, <2 x i64> zeroinitializer, <2 x i32> <i32 0, i32 2>
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ret <2 x i64>%Y
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}
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