llvm-for-llvmta/test/CodeGen/X86/zext-extract_subreg.ll

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2022-04-25 10:02:23 +02:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
define void @t() nounwind ssp {
; CHECK-LABEL: t:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne LBB0_6
; CHECK-NEXT: ## %bb.1: ## %if.end.i
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je LBB0_2
; CHECK-NEXT: LBB0_6: ## %return
; CHECK-NEXT: retq
; CHECK-NEXT: LBB0_2: ## %if.end
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne LBB0_5
; CHECK-NEXT: ## %bb.3: ## %cond.true190
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne LBB0_5
; CHECK-NEXT: ## %bb.4: ## %cond.true225
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: LBB0_5: ## %cond.false205
; CHECK-NEXT: ud2
entry:
br i1 undef, label %return, label %if.end.i
if.end.i: ; preds = %entry
%tmp7.i = load i32, i32* undef, align 4
br i1 undef, label %return, label %if.end
if.end: ; preds = %if.end.i
%tmp138 = select i1 undef, i32 0, i32 %tmp7.i
%tmp867 = zext i32 %tmp138 to i64
br label %while.cond
while.cond: ; preds = %while.body, %if.end
%tmp869 = sub i64 %tmp867, 0
%scale2.0 = trunc i64 %tmp869 to i32
%cmp149 = icmp eq i32 %scale2.0, 0
br i1 %cmp149, label %while.end, label %land.rhs
land.rhs: ; preds = %while.cond
br i1 undef, label %while.body, label %while.end
while.body: ; preds = %land.rhs
br label %while.cond
while.end: ; preds = %land.rhs, %while.cond
br i1 undef, label %cond.false205, label %cond.true190
cond.true190: ; preds = %while.end
br i1 undef, label %cond.false242, label %cond.true225
cond.false205: ; preds = %while.end
unreachable
cond.true225: ; preds = %cond.true190
br i1 undef, label %cond.false280, label %cond.true271
cond.false242: ; preds = %cond.true190
unreachable
cond.true271: ; preds = %cond.true225
unreachable
cond.false280: ; preds = %cond.true225
unreachable
return: ; preds = %if.end.i, %entry
ret void
}