72 lines
2.8 KiB
LLVM
72 lines
2.8 KiB
LLVM
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; RUN: opt -S -instcombine < %s | FileCheck %s
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; ARM64 neon intrinsic variants - <rdar://problem/12349617>
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; REQUIRES: aarch64
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define <4 x i32> @mulByZeroARM64(<4 x i16> %x) nounwind readnone ssp {
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entry:
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%a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> zeroinitializer) nounwind
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ret <4 x i32> %a
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; CHECK: entry:
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; CHECK-NEXT: ret <4 x i32> zeroinitializer
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}
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define <4 x i32> @mulByOneARM64(<4 x i16> %x) nounwind readnone ssp {
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entry:
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%a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
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ret <4 x i32> %a
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; CHECK: entry:
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; CHECK-NEXT: %a = sext <4 x i16> %x to <4 x i32>
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; CHECK-NEXT: ret <4 x i32> %a
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}
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define <4 x i32> @constantMulARM64() nounwind readnone ssp {
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entry:
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%a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
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ret <4 x i32> %a
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; CHECK: entry:
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; CHECK-NEXT: ret <4 x i32> <i32 6, i32 6, i32 6, i32 6>
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}
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define <4 x i32> @constantMulSARM64() nounwind readnone ssp {
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entry:
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%b = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
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ret <4 x i32> %b
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; CHECK: entry:
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; CHECK-NEXT: ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
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}
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define <4 x i32> @constantMulUARM64() nounwind readnone ssp {
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entry:
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%b = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
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ret <4 x i32> %b
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; CHECK: entry:
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; CHECK-NEXT: ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
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}
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define <4 x i32> @complex1ARM64(<4 x i16> %x) nounwind readnone ssp {
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entry:
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%a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) nounwind
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%b = add <4 x i32> zeroinitializer, %a
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ret <4 x i32> %b
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; CHECK: entry:
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; CHECK-NEXT: %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) [[NUW:#[0-9]+]]
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; CHECK-NEXT: ret <4 x i32> %a
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}
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define <4 x i32> @complex2ARM64(<4 x i32> %x) nounwind readnone ssp {
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entry:
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%a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
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%b = add <4 x i32> %x, %a
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ret <4 x i32> %b
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; CHECK: entry:
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; CHECK-NEXT: %b = add <4 x i32> %x, <i32 6, i32 6, i32 6, i32 6>
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; CHECK-NEXT: ret <4 x i32> %b
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}
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declare <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
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declare <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
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; CHECK: attributes #0 = { nounwind readnone ssp }
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; CHECK: attributes #1 = { nounwind readnone }
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; CHECK: attributes [[NUW]] = { nounwind }
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