78 lines
2.2 KiB
LLVM
78 lines
2.2 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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define i5 @XorZextXor(i3 %a) {
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; CHECK-LABEL: @XorZextXor(
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; CHECK-NEXT: [[CAST:%.*]] = zext i3 %a to i5
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; CHECK-NEXT: [[OP2:%.*]] = xor i5 [[CAST]], 15
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; CHECK-NEXT: ret i5 [[OP2]]
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;
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%op1 = xor i3 %a, 3
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%cast = zext i3 %op1 to i5
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%op2 = xor i5 %cast, 12
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ret i5 %op2
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}
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define <2 x i32> @XorZextXorVec(<2 x i1> %a) {
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; CHECK-LABEL: @XorZextXorVec(
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; CHECK-NEXT: [[CAST:%.*]] = zext <2 x i1> %a to <2 x i32>
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; CHECK-NEXT: [[OP2:%.*]] = xor <2 x i32> [[CAST]], <i32 2, i32 1>
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; CHECK-NEXT: ret <2 x i32> [[OP2]]
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;
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%op1 = xor <2 x i1> %a, <i1 true, i1 false>
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%cast = zext <2 x i1> %op1 to <2 x i32>
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%op2 = xor <2 x i32> %cast, <i32 3, i32 1>
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ret <2 x i32> %op2
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}
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define i5 @OrZextOr(i3 %a) {
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; CHECK-LABEL: @OrZextOr(
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; CHECK-NEXT: [[CAST:%.*]] = zext i3 %a to i5
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; CHECK-NEXT: [[OP2:%.*]] = or i5 [[CAST]], 11
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; CHECK-NEXT: ret i5 [[OP2]]
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;
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%op1 = or i3 %a, 3
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%cast = zext i3 %op1 to i5
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%op2 = or i5 %cast, 8
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ret i5 %op2
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}
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define <2 x i32> @OrZextOrVec(<2 x i2> %a) {
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; CHECK-LABEL: @OrZextOrVec(
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; CHECK-NEXT: [[CAST:%.*]] = zext <2 x i2> %a to <2 x i32>
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; CHECK-NEXT: [[OP2:%.*]] = or <2 x i32> [[CAST]], <i32 3, i32 5>
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; CHECK-NEXT: ret <2 x i32> [[OP2]]
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;
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%op1 = or <2 x i2> %a, <i2 2, i2 0>
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%cast = zext <2 x i2> %op1 to <2 x i32>
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%op2 = or <2 x i32> %cast, <i32 1, i32 5>
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ret <2 x i32> %op2
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}
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; Unlike the rest, this case is handled by SimplifyDemandedBits / ShrinkDemandedConstant.
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define i5 @AndZextAnd(i3 %a) {
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; CHECK-LABEL: @AndZextAnd(
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; CHECK-NEXT: [[TMP1:%.*]] = and i3 %a, 2
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; CHECK-NEXT: [[OP2:%.*]] = zext i3 [[TMP1]] to i5
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; CHECK-NEXT: ret i5 [[OP2]]
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;
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%op1 = and i3 %a, 3
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%cast = zext i3 %op1 to i5
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%op2 = and i5 %cast, 14
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ret i5 %op2
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}
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define <2 x i32> @AndZextAndVec(<2 x i8> %a) {
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; CHECK-LABEL: @AndZextAndVec(
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; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> %a, <i8 5, i8 0>
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; CHECK-NEXT: [[OP2:%.*]] = zext <2 x i8> [[TMP1]] to <2 x i32>
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; CHECK-NEXT: ret <2 x i32> [[OP2]]
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;
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%op1 = and <2 x i8> %a, <i8 7, i8 0>
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%cast = zext <2 x i8> %op1 to <2 x i32>
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%op2 = and <2 x i32> %cast, <i32 261, i32 1>
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ret <2 x i32> %op2
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}
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