59 lines
2.1 KiB
LLVM
59 lines
2.1 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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; int test0(int a) { return (a + (~(a & 0x55555555) + 1)); }
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define i32 @test0(i32 %a0) {
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; CHECK-LABEL: @test0(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A0:%.*]], -1431655766
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; CHECK-NEXT: ret i32 [[TMP1]]
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;
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%1 = and i32 %a0, 1431655765
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%2 = xor i32 %1, -1
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%3 = add nsw i32 %2, 1
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%4 = add nsw i32 %a0, %3
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ret i32 %4
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}
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define <4 x i32> @test0_vec(<4 x i32> %a0) {
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; CHECK-LABEL: @test0_vec(
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; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i32> [[A0:%.*]], <i32 -1431655766, i32 -1431655766, i32 -1431655766, i32 -1431655766>
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; CHECK-NEXT: ret <4 x i32> [[TMP1]]
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;
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%1 = and <4 x i32> %a0, <i32 1431655765, i32 1431655765, i32 1431655765, i32 1431655765>
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%2 = xor <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1>
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%3 = add nsw <4 x i32> %2, <i32 1, i32 1, i32 1, i32 1>
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%4 = add nsw <4 x i32> %a0, %3
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ret <4 x i32> %4
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}
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; int test1(int a) { return (a + (~((a >> 1) & 0x55555555) + 1)); }
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define i32 @test1(i32 %a0) {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[A0:%.*]], 1
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 1431655765
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; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[A0]], [[TMP2]]
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; CHECK-NEXT: ret i32 [[TMP3]]
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;
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%1 = ashr i32 %a0, 1
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%2 = and i32 %1, 1431655765
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%3 = xor i32 %2, -1
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%4 = add nsw i32 %3, 1
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%5 = add nsw i32 %a0, %4
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ret i32 %5
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}
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define <4 x i32> @test1_vec(<4 x i32> %a0) {
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; CHECK-LABEL: @test1_vec(
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; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i32> [[A0:%.*]], <i32 1, i32 1, i32 1, i32 1>
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; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i32> [[TMP1]], <i32 1431655765, i32 1431655765, i32 1431655765, i32 1431655765>
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; CHECK-NEXT: [[TMP3:%.*]] = sub <4 x i32> [[A0]], [[TMP2]]
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; CHECK-NEXT: ret <4 x i32> [[TMP3]]
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;
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%1 = ashr <4 x i32> %a0, <i32 1, i32 1, i32 1, i32 1>
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%2 = and <4 x i32> %1, <i32 1431655765, i32 1431655765, i32 1431655765, i32 1431655765>
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%3 = xor <4 x i32> %2, <i32 -1, i32 -1, i32 -1, i32 -1>
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%4 = add nsw <4 x i32> %3, <i32 1, i32 1, i32 1, i32 1>
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%5 = add nsw <4 x i32> %a0, %4
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ret <4 x i32> %5
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}
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