439 lines
13 KiB
C
439 lines
13 KiB
C
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//===--- AMDGPU.h - Declare AMDGPU target feature support -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares AMDGPU TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_AMDGPU_H
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#define LLVM_CLANG_LIB_BASIC_TARGETS_AMDGPU_H
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#include "clang/Basic/TargetID.h"
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#include "clang/Basic/TargetInfo.h"
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#include "clang/Basic/TargetOptions.h"
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#include "llvm/ADT/StringSet.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/TargetParser.h"
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namespace clang {
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namespace targets {
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class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo {
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static const Builtin::Info BuiltinInfo[];
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static const char *const GCCRegNames[];
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enum AddrSpace {
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Generic = 0,
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Global = 1,
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Local = 3,
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Constant = 4,
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Private = 5
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};
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static const LangASMap AMDGPUDefIsGenMap;
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static const LangASMap AMDGPUDefIsPrivMap;
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llvm::AMDGPU::GPUKind GPUKind;
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unsigned GPUFeatures;
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unsigned WavefrontSize;
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/// Target ID is device name followed by optional feature name postfixed
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/// by plus or minus sign delimitted by colon, e.g. gfx908:xnack+:sramecc-.
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/// If the target ID contains feature+, map it to true.
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/// If the target ID contains feature-, map it to false.
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/// If the target ID does not contain a feature (default), do not map it.
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llvm::StringMap<bool> OffloadArchFeatures;
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std::string TargetID;
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bool hasFP64() const {
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return getTriple().getArch() == llvm::Triple::amdgcn ||
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!!(GPUFeatures & llvm::AMDGPU::FEATURE_FP64);
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}
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/// Has fast fma f32
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bool hasFastFMAF() const {
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return !!(GPUFeatures & llvm::AMDGPU::FEATURE_FAST_FMA_F32);
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}
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/// Has fast fma f64
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bool hasFastFMA() const {
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return getTriple().getArch() == llvm::Triple::amdgcn;
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}
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bool hasFMAF() const {
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return getTriple().getArch() == llvm::Triple::amdgcn ||
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!!(GPUFeatures & llvm::AMDGPU::FEATURE_FMA);
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}
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bool hasFullRateDenormalsF32() const {
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return !!(GPUFeatures & llvm::AMDGPU::FEATURE_FAST_DENORMAL_F32);
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}
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bool hasLDEXPF() const {
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return getTriple().getArch() == llvm::Triple::amdgcn ||
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!!(GPUFeatures & llvm::AMDGPU::FEATURE_LDEXP);
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}
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static bool isAMDGCN(const llvm::Triple &TT) {
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return TT.getArch() == llvm::Triple::amdgcn;
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}
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static bool isR600(const llvm::Triple &TT) {
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return TT.getArch() == llvm::Triple::r600;
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}
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public:
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AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
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void setAddressSpaceMap(bool DefaultIsPrivate);
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void adjust(LangOptions &Opts) override;
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uint64_t getPointerWidthV(unsigned AddrSpace) const override {
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if (isR600(getTriple()))
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return 32;
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if (AddrSpace == Private || AddrSpace == Local)
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return 32;
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return 64;
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}
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uint64_t getPointerAlignV(unsigned AddrSpace) const override {
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return getPointerWidthV(AddrSpace);
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}
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uint64_t getMaxPointerWidth() const override {
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return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32;
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}
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const char *getClobbers() const override { return ""; }
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ArrayRef<const char *> getGCCRegNames() const override;
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ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
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return None;
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}
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/// Accepted register names: (n, m is unsigned integer, n < m)
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/// v
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/// s
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/// a
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/// {vn}, {v[n]}
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/// {sn}, {s[n]}
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/// {an}, {a[n]}
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/// {S} , where S is a special register name
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////{v[n:m]}
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/// {s[n:m]}
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/// {a[n:m]}
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bool validateAsmConstraint(const char *&Name,
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TargetInfo::ConstraintInfo &Info) const override {
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static const ::llvm::StringSet<> SpecialRegs({
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"exec", "vcc", "flat_scratch", "m0", "scc", "tba", "tma",
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"flat_scratch_lo", "flat_scratch_hi", "vcc_lo", "vcc_hi", "exec_lo",
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"exec_hi", "tma_lo", "tma_hi", "tba_lo", "tba_hi",
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});
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switch (*Name) {
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case 'I':
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Info.setRequiresImmediate(-16, 64);
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return true;
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case 'J':
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Info.setRequiresImmediate(-32768, 32767);
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return true;
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case 'A':
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case 'B':
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case 'C':
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Info.setRequiresImmediate();
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return true;
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default:
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break;
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}
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StringRef S(Name);
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if (S == "DA" || S == "DB") {
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Name++;
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Info.setRequiresImmediate();
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return true;
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}
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bool HasLeftParen = false;
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if (S.front() == '{') {
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HasLeftParen = true;
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S = S.drop_front();
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}
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if (S.empty())
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return false;
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if (S.front() != 'v' && S.front() != 's' && S.front() != 'a') {
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if (!HasLeftParen)
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return false;
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auto E = S.find('}');
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if (!SpecialRegs.count(S.substr(0, E)))
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return false;
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S = S.drop_front(E + 1);
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if (!S.empty())
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return false;
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// Found {S} where S is a special register.
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Info.setAllowsRegister();
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Name = S.data() - 1;
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return true;
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}
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S = S.drop_front();
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if (!HasLeftParen) {
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if (!S.empty())
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return false;
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// Found s, v or a.
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Info.setAllowsRegister();
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Name = S.data() - 1;
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return true;
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}
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bool HasLeftBracket = false;
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if (!S.empty() && S.front() == '[') {
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HasLeftBracket = true;
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S = S.drop_front();
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}
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unsigned long long N;
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if (S.empty() || consumeUnsignedInteger(S, 10, N))
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return false;
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if (!S.empty() && S.front() == ':') {
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if (!HasLeftBracket)
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return false;
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S = S.drop_front();
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unsigned long long M;
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if (consumeUnsignedInteger(S, 10, M) || N >= M)
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return false;
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}
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if (HasLeftBracket) {
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if (S.empty() || S.front() != ']')
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return false;
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S = S.drop_front();
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}
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if (S.empty() || S.front() != '}')
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return false;
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S = S.drop_front();
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if (!S.empty())
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return false;
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// Found {vn}, {sn}, {an}, {v[n]}, {s[n]}, {a[n]}, {v[n:m]}, {s[n:m]}
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// or {a[n:m]}.
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Info.setAllowsRegister();
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Name = S.data() - 1;
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return true;
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}
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// \p Constraint will be left pointing at the last character of
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// the constraint. In practice, it won't be changed unless the
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// constraint is longer than one character.
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std::string convertConstraint(const char *&Constraint) const override {
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StringRef S(Constraint);
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if (S == "DA" || S == "DB") {
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return std::string("^") + std::string(Constraint++, 2);
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}
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const char *Begin = Constraint;
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TargetInfo::ConstraintInfo Info("", "");
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if (validateAsmConstraint(Constraint, Info))
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return std::string(Begin).substr(0, Constraint - Begin + 1);
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Constraint = Begin;
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return std::string(1, *Constraint);
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}
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bool
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initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
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StringRef CPU,
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const std::vector<std::string> &FeatureVec) const override;
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ArrayRef<Builtin::Info> getTargetBuiltins() const override;
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bool useFP16ConversionIntrinsics() const override { return false; }
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void getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const override;
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BuiltinVaListKind getBuiltinVaListKind() const override {
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return TargetInfo::CharPtrBuiltinVaList;
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}
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bool isValidCPUName(StringRef Name) const override {
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if (getTriple().getArch() == llvm::Triple::amdgcn)
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return llvm::AMDGPU::parseArchAMDGCN(Name) != llvm::AMDGPU::GK_NONE;
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return llvm::AMDGPU::parseArchR600(Name) != llvm::AMDGPU::GK_NONE;
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}
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void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
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bool setCPU(const std::string &Name) override {
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if (getTriple().getArch() == llvm::Triple::amdgcn) {
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GPUKind = llvm::AMDGPU::parseArchAMDGCN(Name);
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GPUFeatures = llvm::AMDGPU::getArchAttrAMDGCN(GPUKind);
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} else {
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GPUKind = llvm::AMDGPU::parseArchR600(Name);
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GPUFeatures = llvm::AMDGPU::getArchAttrR600(GPUKind);
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}
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return GPUKind != llvm::AMDGPU::GK_NONE;
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}
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void setSupportedOpenCLOpts() override {
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auto &Opts = getSupportedOpenCLOpts();
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Opts["cl_clang_storage_class_specifiers"] = true;
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Opts["__cl_clang_variadic_functions"] = true;
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Opts["__cl_clang_function_pointers"] = true;
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bool IsAMDGCN = isAMDGCN(getTriple());
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Opts["cl_khr_fp64"] = hasFP64();
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if (IsAMDGCN || GPUKind >= llvm::AMDGPU::GK_CEDAR) {
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Opts["cl_khr_byte_addressable_store"] = true;
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Opts["cl_khr_global_int32_base_atomics"] = true;
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Opts["cl_khr_global_int32_extended_atomics"] = true;
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Opts["cl_khr_local_int32_base_atomics"] = true;
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Opts["cl_khr_local_int32_extended_atomics"] = true;
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}
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if (IsAMDGCN) {
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Opts["cl_khr_fp16"] = true;
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Opts["cl_khr_int64_base_atomics"] = true;
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Opts["cl_khr_int64_extended_atomics"] = true;
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Opts["cl_khr_mipmap_image"] = true;
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Opts["cl_khr_mipmap_image_writes"] = true;
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Opts["cl_khr_subgroups"] = true;
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Opts["cl_khr_3d_image_writes"] = true;
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Opts["cl_amd_media_ops"] = true;
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Opts["cl_amd_media_ops2"] = true;
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}
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}
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LangAS getOpenCLTypeAddrSpace(OpenCLTypeKind TK) const override {
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switch (TK) {
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case OCLTK_Image:
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return LangAS::opencl_constant;
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case OCLTK_ClkEvent:
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case OCLTK_Queue:
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case OCLTK_ReserveID:
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return LangAS::opencl_global;
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default:
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return TargetInfo::getOpenCLTypeAddrSpace(TK);
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}
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}
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LangAS getOpenCLBuiltinAddressSpace(unsigned AS) const override {
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switch (AS) {
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case 0:
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return LangAS::opencl_generic;
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case 1:
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return LangAS::opencl_global;
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case 3:
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return LangAS::opencl_local;
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case 4:
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return LangAS::opencl_constant;
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case 5:
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return LangAS::opencl_private;
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default:
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return getLangASFromTargetAS(AS);
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}
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}
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LangAS getCUDABuiltinAddressSpace(unsigned AS) const override {
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return LangAS::Default;
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}
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llvm::Optional<LangAS> getConstantAddressSpace() const override {
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return getLangASFromTargetAS(Constant);
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}
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/// \returns Target specific vtbl ptr address space.
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unsigned getVtblPtrAddressSpace() const override {
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return static_cast<unsigned>(Constant);
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}
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/// \returns If a target requires an address within a target specific address
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/// space \p AddressSpace to be converted in order to be used, then return the
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/// corresponding target specific DWARF address space.
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///
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/// \returns Otherwise return None and no conversion will be emitted in the
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/// DWARF.
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Optional<unsigned>
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getDWARFAddressSpace(unsigned AddressSpace) const override {
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const unsigned DWARF_Private = 1;
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const unsigned DWARF_Local = 2;
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if (AddressSpace == Private) {
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return DWARF_Private;
|
||
|
|
} else if (AddressSpace == Local) {
|
||
|
|
return DWARF_Local;
|
||
|
|
} else {
|
||
|
|
return None;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
|
||
|
|
switch (CC) {
|
||
|
|
default:
|
||
|
|
return CCCR_Warning;
|
||
|
|
case CC_C:
|
||
|
|
case CC_OpenCLKernel:
|
||
|
|
return CCCR_OK;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
// In amdgcn target the null pointer in global, constant, and generic
|
||
|
|
// address space has value 0 but in private and local address space has
|
||
|
|
// value ~0.
|
||
|
|
uint64_t getNullPointerValue(LangAS AS) const override {
|
||
|
|
// FIXME: Also should handle region.
|
||
|
|
return (AS == LangAS::opencl_local || AS == LangAS::opencl_private)
|
||
|
|
? ~0 : 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void setAuxTarget(const TargetInfo *Aux) override;
|
||
|
|
|
||
|
|
bool hasExtIntType() const override { return true; }
|
||
|
|
|
||
|
|
// Record offload arch features since they are needed for defining the
|
||
|
|
// pre-defined macros.
|
||
|
|
bool handleTargetFeatures(std::vector<std::string> &Features,
|
||
|
|
DiagnosticsEngine &Diags) override {
|
||
|
|
auto TargetIDFeatures =
|
||
|
|
getAllPossibleTargetIDFeatures(getTriple(), getArchNameAMDGCN(GPUKind));
|
||
|
|
llvm::for_each(Features, [&](const auto &F) {
|
||
|
|
assert(F.front() == '+' || F.front() == '-');
|
||
|
|
if (F == "+wavefrontsize64")
|
||
|
|
WavefrontSize = 64;
|
||
|
|
bool IsOn = F.front() == '+';
|
||
|
|
StringRef Name = StringRef(F).drop_front();
|
||
|
|
if (llvm::find(TargetIDFeatures, Name) == TargetIDFeatures.end())
|
||
|
|
return;
|
||
|
|
assert(OffloadArchFeatures.find(Name) == OffloadArchFeatures.end());
|
||
|
|
OffloadArchFeatures[Name] = IsOn;
|
||
|
|
});
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
Optional<std::string> getTargetID() const override {
|
||
|
|
if (!isAMDGCN(getTriple()))
|
||
|
|
return llvm::None;
|
||
|
|
// When -target-cpu is not set, we assume generic code that it is valid
|
||
|
|
// for all GPU and use an empty string as target ID to represent that.
|
||
|
|
if (GPUKind == llvm::AMDGPU::GK_NONE)
|
||
|
|
return std::string("");
|
||
|
|
return getCanonicalTargetID(getArchNameAMDGCN(GPUKind),
|
||
|
|
OffloadArchFeatures);
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
} // namespace targets
|
||
|
|
} // namespace clang
|
||
|
|
|
||
|
|
#endif // LLVM_CLANG_LIB_BASIC_TARGETS_AMDGPU_H
|