; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare void @llvm.riscv.vsse.nxv1i32( <vscale x 1 x i32>, <vscale x 1 x i32>*, i32, i32); define void @intrinsic_vsse_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu ; CHECK-NEXT: vsse32.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv1i32( <vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv1i32( <vscale x 1 x i32>, <vscale x 1 x i32>*, i32, <vscale x 1 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu ; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv1i32( <vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv2i32( <vscale x 2 x i32>, <vscale x 2 x i32>*, i32, i32); define void @intrinsic_vsse_v_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu ; CHECK-NEXT: vsse32.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv2i32( <vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv2i32( <vscale x 2 x i32>, <vscale x 2 x i32>*, i32, <vscale x 2 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu ; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv2i32( <vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv4i32( <vscale x 4 x i32>, <vscale x 4 x i32>*, i32, i32); define void @intrinsic_vsse_v_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu ; CHECK-NEXT: vsse32.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv4i32( <vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv4i32( <vscale x 4 x i32>, <vscale x 4 x i32>*, i32, <vscale x 4 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu ; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv4i32( <vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv8i32( <vscale x 8 x i32>, <vscale x 8 x i32>*, i32, i32); define void @intrinsic_vsse_v_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu ; CHECK-NEXT: vsse32.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv8i32( <vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv8i32( <vscale x 8 x i32>, <vscale x 8 x i32>*, i32, <vscale x 8 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu ; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv8i32( <vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv16i32( <vscale x 16 x i32>, <vscale x 16 x i32>*, i32, i32); define void @intrinsic_vsse_v_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m8,ta,mu ; CHECK-NEXT: vsse32.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv16i32( <vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv16i32( <vscale x 16 x i32>, <vscale x 16 x i32>*, i32, <vscale x 16 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m8,ta,mu ; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv16i32( <vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv1f32( <vscale x 1 x float>, <vscale x 1 x float>*, i32, i32); define void @intrinsic_vsse_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu ; CHECK-NEXT: vsse32.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv1f32( <vscale x 1 x float> %0, <vscale x 1 x float>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv1f32( <vscale x 1 x float>, <vscale x 1 x float>*, i32, <vscale x 1 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu ; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv1f32( <vscale x 1 x float> %0, <vscale x 1 x float>* %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv2f32( <vscale x 2 x float>, <vscale x 2 x float>*, i32, i32); define void @intrinsic_vsse_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu ; CHECK-NEXT: vsse32.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv2f32( <vscale x 2 x float> %0, <vscale x 2 x float>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv2f32( <vscale x 2 x float>, <vscale x 2 x float>*, i32, <vscale x 2 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu ; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv2f32( <vscale x 2 x float> %0, <vscale x 2 x float>* %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv4f32( <vscale x 4 x float>, <vscale x 4 x float>*, i32, i32); define void @intrinsic_vsse_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu ; CHECK-NEXT: vsse32.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv4f32( <vscale x 4 x float> %0, <vscale x 4 x float>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv4f32( <vscale x 4 x float>, <vscale x 4 x float>*, i32, <vscale x 4 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu ; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv4f32( <vscale x 4 x float> %0, <vscale x 4 x float>* %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv8f32( <vscale x 8 x float>, <vscale x 8 x float>*, i32, i32); define void @intrinsic_vsse_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu ; CHECK-NEXT: vsse32.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv8f32( <vscale x 8 x float> %0, <vscale x 8 x float>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv8f32( <vscale x 8 x float>, <vscale x 8 x float>*, i32, <vscale x 8 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu ; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv8f32( <vscale x 8 x float> %0, <vscale x 8 x float>* %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv16f32( <vscale x 16 x float>, <vscale x 16 x float>*, i32, i32); define void @intrinsic_vsse_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m8,ta,mu ; CHECK-NEXT: vsse32.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv16f32( <vscale x 16 x float> %0, <vscale x 16 x float>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv16f32( <vscale x 16 x float>, <vscale x 16 x float>*, i32, <vscale x 16 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m8,ta,mu ; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv16f32( <vscale x 16 x float> %0, <vscale x 16 x float>* %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv1i16( <vscale x 1 x i16>, <vscale x 1 x i16>*, i32, i32); define void @intrinsic_vsse_v_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv1i16( <vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv1i16( <vscale x 1 x i16>, <vscale x 1 x i16>*, i32, <vscale x 1 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv1i16( <vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv2i16( <vscale x 2 x i16>, <vscale x 2 x i16>*, i32, i32); define void @intrinsic_vsse_v_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv2i16( <vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv2i16( <vscale x 2 x i16>, <vscale x 2 x i16>*, i32, <vscale x 2 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv2i16( <vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv4i16( <vscale x 4 x i16>, <vscale x 4 x i16>*, i32, i32); define void @intrinsic_vsse_v_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv4i16( <vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv4i16( <vscale x 4 x i16>, <vscale x 4 x i16>*, i32, <vscale x 4 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv4i16( <vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv8i16( <vscale x 8 x i16>, <vscale x 8 x i16>*, i32, i32); define void @intrinsic_vsse_v_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv8i16( <vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv8i16( <vscale x 8 x i16>, <vscale x 8 x i16>*, i32, <vscale x 8 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv8i16( <vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv16i16( <vscale x 16 x i16>, <vscale x 16 x i16>*, i32, i32); define void @intrinsic_vsse_v_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv16i16( <vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv16i16( <vscale x 16 x i16>, <vscale x 16 x i16>*, i32, <vscale x 16 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv16i16( <vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv32i16( <vscale x 32 x i16>, <vscale x 32 x i16>*, i32, i32); define void @intrinsic_vsse_v_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m8,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv32i16( <vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv32i16( <vscale x 32 x i16>, <vscale x 32 x i16>*, i32, <vscale x 32 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m8,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv32i16( <vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv1f16( <vscale x 1 x half>, <vscale x 1 x half>*, i32, i32); define void @intrinsic_vsse_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv1f16( <vscale x 1 x half> %0, <vscale x 1 x half>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv1f16( <vscale x 1 x half>, <vscale x 1 x half>*, i32, <vscale x 1 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv1f16( <vscale x 1 x half> %0, <vscale x 1 x half>* %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv2f16( <vscale x 2 x half>, <vscale x 2 x half>*, i32, i32); define void @intrinsic_vsse_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv2f16( <vscale x 2 x half> %0, <vscale x 2 x half>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv2f16( <vscale x 2 x half>, <vscale x 2 x half>*, i32, <vscale x 2 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv2f16( <vscale x 2 x half> %0, <vscale x 2 x half>* %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv4f16( <vscale x 4 x half>, <vscale x 4 x half>*, i32, i32); define void @intrinsic_vsse_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv4f16( <vscale x 4 x half> %0, <vscale x 4 x half>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv4f16( <vscale x 4 x half>, <vscale x 4 x half>*, i32, <vscale x 4 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv4f16( <vscale x 4 x half> %0, <vscale x 4 x half>* %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv8f16( <vscale x 8 x half>, <vscale x 8 x half>*, i32, i32); define void @intrinsic_vsse_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv8f16( <vscale x 8 x half> %0, <vscale x 8 x half>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv8f16( <vscale x 8 x half>, <vscale x 8 x half>*, i32, <vscale x 8 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv8f16( <vscale x 8 x half> %0, <vscale x 8 x half>* %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv16f16( <vscale x 16 x half>, <vscale x 16 x half>*, i32, i32); define void @intrinsic_vsse_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv16f16( <vscale x 16 x half> %0, <vscale x 16 x half>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv16f16( <vscale x 16 x half>, <vscale x 16 x half>*, i32, <vscale x 16 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv16f16( <vscale x 16 x half> %0, <vscale x 16 x half>* %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv32f16( <vscale x 32 x half>, <vscale x 32 x half>*, i32, i32); define void @intrinsic_vsse_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m8,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv32f16( <vscale x 32 x half> %0, <vscale x 32 x half>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv32f16( <vscale x 32 x half>, <vscale x 32 x half>*, i32, <vscale x 32 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m8,ta,mu ; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv32f16( <vscale x 32 x half> %0, <vscale x 32 x half>* %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv1i8( <vscale x 1 x i8>, <vscale x 1 x i8>*, i32, i32); define void @intrinsic_vsse_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu ; CHECK-NEXT: vsse8.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv1i8( <vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv1i8( <vscale x 1 x i8>, <vscale x 1 x i8>*, i32, <vscale x 1 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu ; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv1i8( <vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv2i8( <vscale x 2 x i8>, <vscale x 2 x i8>*, i32, i32); define void @intrinsic_vsse_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu ; CHECK-NEXT: vsse8.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv2i8( <vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv2i8( <vscale x 2 x i8>, <vscale x 2 x i8>*, i32, <vscale x 2 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu ; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv2i8( <vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv4i8( <vscale x 4 x i8>, <vscale x 4 x i8>*, i32, i32); define void @intrinsic_vsse_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu ; CHECK-NEXT: vsse8.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv4i8( <vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv4i8( <vscale x 4 x i8>, <vscale x 4 x i8>*, i32, <vscale x 4 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu ; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv4i8( <vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv8i8( <vscale x 8 x i8>, <vscale x 8 x i8>*, i32, i32); define void @intrinsic_vsse_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu ; CHECK-NEXT: vsse8.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv8i8( <vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv8i8( <vscale x 8 x i8>, <vscale x 8 x i8>*, i32, <vscale x 8 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu ; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv8i8( <vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv16i8( <vscale x 16 x i8>, <vscale x 16 x i8>*, i32, i32); define void @intrinsic_vsse_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu ; CHECK-NEXT: vsse8.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv16i8( <vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv16i8( <vscale x 16 x i8>, <vscale x 16 x i8>*, i32, <vscale x 16 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu ; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv16i8( <vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv32i8( <vscale x 32 x i8>, <vscale x 32 x i8>*, i32, i32); define void @intrinsic_vsse_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m4,ta,mu ; CHECK-NEXT: vsse8.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv32i8( <vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv32i8( <vscale x 32 x i8>, <vscale x 32 x i8>*, i32, <vscale x 32 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m4,ta,mu ; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv32i8( <vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, i32 %2, <vscale x 32 x i1> %3, i32 %4) ret void } declare void @llvm.riscv.vsse.nxv64i8( <vscale x 64 x i8>, <vscale x 64 x i8>*, i32, i32); define void @intrinsic_vsse_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8>* %1, i32 %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsse_v_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m8,ta,mu ; CHECK-NEXT: vsse8.v v8, (a0), a1 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.nxv64i8( <vscale x 64 x i8> %0, <vscale x 64 x i8>* %1, i32 %2, i32 %3) ret void } declare void @llvm.riscv.vsse.mask.nxv64i8( <vscale x 64 x i8>, <vscale x 64 x i8>*, i32, <vscale x 64 x i1>, i32); define void @intrinsic_vsse_mask_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8>* %1, i32 %2, <vscale x 64 x i1> %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsse_mask_v_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m8,ta,mu ; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsse.mask.nxv64i8( <vscale x 64 x i8> %0, <vscale x 64 x i8>* %1, i32 %2, <vscale x 64 x i1> %3, i32 %4) ret void }