937 lines
40 KiB
C++
937 lines
40 KiB
C++
//===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that ARM uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
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#define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
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#include "MCTargetDesc/ARMBaseInfo.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/ISDOpcodes.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/InlineAsm.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Support/MachineValueType.h"
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#include <utility>
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namespace llvm {
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class ARMSubtarget;
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class DataLayout;
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class FastISel;
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class FunctionLoweringInfo;
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class GlobalValue;
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class InstrItineraryData;
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class Instruction;
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class MachineBasicBlock;
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class MachineInstr;
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class SelectionDAG;
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class TargetLibraryInfo;
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class TargetMachine;
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class TargetRegisterInfo;
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class VectorType;
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namespace ARMISD {
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// ARM Specific DAG Nodes
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enum NodeType : unsigned {
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// Start the numbering where the builtin ops and target ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
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// TargetExternalSymbol, and TargetGlobalAddress.
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WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
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// PIC mode.
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WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
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// Add pseudo op to model memcpy for struct byval.
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COPY_STRUCT_BYVAL,
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CALL, // Function call.
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CALL_PRED, // Function call that's predicable.
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CALL_NOLINK, // Function call with branch not branch-and-link.
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tSECALL, // CMSE non-secure function call.
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BRCOND, // Conditional branch.
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BR_JT, // Jumptable branch.
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BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
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RET_FLAG, // Return with a flag operand.
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SERET_FLAG, // CMSE Entry function return with a flag operand.
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INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
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PIC_ADD, // Add with a PC operand and a PIC label.
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ASRL, // MVE long arithmetic shift right.
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LSRL, // MVE long shift right.
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LSLL, // MVE long shift left.
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CMP, // ARM compare instructions.
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CMN, // ARM CMN instructions.
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CMPZ, // ARM compare that sets only Z flag.
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CMPFP, // ARM VFP compare instruction, sets FPSCR.
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CMPFPE, // ARM VFP signalling compare instruction, sets FPSCR.
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CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
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CMPFPEw0, // ARM VFP signalling compare against zero instruction, sets FPSCR.
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FMSTAT, // ARM fmstat instruction.
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CMOV, // ARM conditional move instructions.
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SUBS, // Flag-setting subtraction.
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SSAT, // Signed saturation
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USAT, // Unsigned saturation
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BCC_i64,
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SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
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SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
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RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
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ADDC, // Add with carry
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ADDE, // Add using carry
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SUBC, // Sub with carry
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SUBE, // Sub using carry
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LSLS, // Shift left producing carry
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VMOVRRD, // double to two gprs.
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VMOVDRR, // Two gprs to double.
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VMOVSR, // move gpr to single, used for f32 literal constructed in a gpr
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EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
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EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
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EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
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TC_RETURN, // Tail call return pseudo.
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THREAD_POINTER,
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DYN_ALLOC, // Dynamic allocation on the stack.
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MEMBARRIER_MCR, // Memory barrier (MCR)
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PRELOAD, // Preload
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WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
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WIN__DBZCHK, // Windows' divide by zero check
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WLS, // Low-overhead loops, While Loop Start
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LOOP_DEC, // Really a part of LE, performs the sub
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LE, // Low-overhead loops, Loop End
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PREDICATE_CAST, // Predicate cast for MVE i1 types
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VECTOR_REG_CAST, // Reinterpret the current contents of a vector register
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VCMP, // Vector compare.
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VCMPZ, // Vector compare to zero.
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VTST, // Vector test bits.
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// Vector shift by vector
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VSHLs, // ...left/right by signed
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VSHLu, // ...left/right by unsigned
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// Vector shift by immediate:
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VSHLIMM, // ...left
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VSHRsIMM, // ...right (signed)
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VSHRuIMM, // ...right (unsigned)
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// Vector rounding shift by immediate:
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VRSHRsIMM, // ...right (signed)
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VRSHRuIMM, // ...right (unsigned)
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VRSHRNIMM, // ...right narrow
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// Vector saturating shift by immediate:
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VQSHLsIMM, // ...left (signed)
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VQSHLuIMM, // ...left (unsigned)
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VQSHLsuIMM, // ...left (signed to unsigned)
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VQSHRNsIMM, // ...right narrow (signed)
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VQSHRNuIMM, // ...right narrow (unsigned)
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VQSHRNsuIMM, // ...right narrow (signed to unsigned)
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// Vector saturating rounding shift by immediate:
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VQRSHRNsIMM, // ...right narrow (signed)
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VQRSHRNuIMM, // ...right narrow (unsigned)
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VQRSHRNsuIMM, // ...right narrow (signed to unsigned)
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// Vector shift and insert:
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VSLIIMM, // ...left
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VSRIIMM, // ...right
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// Vector get lane (VMOV scalar to ARM core register)
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// (These are used for 8- and 16-bit element types only.)
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VGETLANEu, // zero-extend vector extract element
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VGETLANEs, // sign-extend vector extract element
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// Vector move immediate and move negated immediate:
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VMOVIMM,
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VMVNIMM,
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// Vector move f32 immediate:
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VMOVFPIMM,
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// Move H <-> R, clearing top 16 bits
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VMOVrh,
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VMOVhr,
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// Vector duplicate:
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VDUP,
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VDUPLANE,
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// Vector shuffles:
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VEXT, // extract
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VREV64, // reverse elements within 64-bit doublewords
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VREV32, // reverse elements within 32-bit words
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VREV16, // reverse elements within 16-bit halfwords
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VZIP, // zip (interleave)
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VUZP, // unzip (deinterleave)
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VTRN, // transpose
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VTBL1, // 1-register shuffle with mask
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VTBL2, // 2-register shuffle with mask
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VMOVN, // MVE vmovn
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// MVE Saturating truncates
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VQMOVNs, // Vector (V) Saturating (Q) Move and Narrow (N), signed (s)
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VQMOVNu, // Vector (V) Saturating (Q) Move and Narrow (N), unsigned (u)
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// MVE float <> half converts
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VCVTN, // MVE vcvt f32 -> f16, truncating into either the bottom or top lanes
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VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes
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// Vector multiply long:
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VMULLs, // ...signed
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VMULLu, // ...unsigned
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VQDMULH, // MVE vqdmulh instruction
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// MVE reductions
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VADDVs, // sign- or zero-extend the elements of a vector to i32,
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VADDVu, // add them all together, and return an i32 of their sum
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VADDVps, // Same as VADDV[su] but with a v4i1 predicate mask
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VADDVpu,
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VADDLVs, // sign- or zero-extend elements to i64 and sum, returning
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VADDLVu, // the low and high 32-bit halves of the sum
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VADDLVAs, // Same as VADDLV[su] but also add an input accumulator
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VADDLVAu, // provided as low and high halves
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VADDLVps, // Same as VADDLV[su] but with a v4i1 predicate mask
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VADDLVpu,
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VADDLVAps, // Same as VADDLVp[su] but with a v4i1 predicate mask
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VADDLVApu,
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VMLAVs, // sign- or zero-extend the elements of two vectors to i32, multiply them
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VMLAVu, // and add the results together, returning an i32 of their sum
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VMLAVps, // Same as VMLAV[su] with a v4i1 predicate mask
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VMLAVpu,
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VMLALVs, // Same as VMLAV but with i64, returning the low and
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VMLALVu, // high 32-bit halves of the sum
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VMLALVps, // Same as VMLALV[su] with a v4i1 predicate mask
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VMLALVpu,
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VMLALVAs, // Same as VMLALV but also add an input accumulator
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VMLALVAu, // provided as low and high halves
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VMLALVAps, // Same as VMLALVA[su] with a v4i1 predicate mask
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VMLALVApu,
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VMINVu, // Find minimum unsigned value of a vector and register
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VMINVs, // Find minimum signed value of a vector and register
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VMAXVu, // Find maximum unsigned value of a vector and register
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VMAXVs, // Find maximum signed value of a vector and register
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SMULWB, // Signed multiply word by half word, bottom
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SMULWT, // Signed multiply word by half word, top
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UMLAL, // 64bit Unsigned Accumulate Multiply
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SMLAL, // 64bit Signed Accumulate Multiply
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UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply
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SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16
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SMLALBT, // 64-bit signed accumulate multiply bottom, top 16
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SMLALTB, // 64-bit signed accumulate multiply top, bottom 16
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SMLALTT, // 64-bit signed accumulate multiply top, top 16
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SMLALD, // Signed multiply accumulate long dual
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SMLALDX, // Signed multiply accumulate long dual exchange
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SMLSLD, // Signed multiply subtract long dual
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SMLSLDX, // Signed multiply subtract long dual exchange
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SMMLAR, // Signed multiply long, round and add
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SMMLSR, // Signed multiply long, subtract and round
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// Single Lane QADD8 and QADD16. Only the bottom lane. That's what the b stands for.
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QADD8b,
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QSUB8b,
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QADD16b,
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QSUB16b,
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// Operands of the standard BUILD_VECTOR node are not legalized, which
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// is fine if BUILD_VECTORs are always lowered to shuffles or other
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// operations, but for ARM some BUILD_VECTORs are legal as-is and their
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// operands need to be legalized. Define an ARM-specific version of
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// BUILD_VECTOR for this purpose.
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BUILD_VECTOR,
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// Bit-field insert
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BFI,
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// Vector OR with immediate
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VORRIMM,
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// Vector AND with NOT of immediate
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VBICIMM,
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// Pseudo vector bitwise select
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VBSP,
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// Pseudo-instruction representing a memory copy using ldm/stm
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// instructions.
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MEMCPY,
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// V8.1MMainline condition select
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CSINV, // Conditional select invert.
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CSNEG, // Conditional select negate.
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CSINC, // Conditional select increment.
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// Vector load N-element structure to all lanes:
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VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
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VLD2DUP,
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VLD3DUP,
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VLD4DUP,
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// NEON loads with post-increment base updates:
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VLD1_UPD,
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VLD2_UPD,
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VLD3_UPD,
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VLD4_UPD,
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VLD2LN_UPD,
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VLD3LN_UPD,
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VLD4LN_UPD,
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VLD1DUP_UPD,
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VLD2DUP_UPD,
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VLD3DUP_UPD,
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VLD4DUP_UPD,
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// NEON stores with post-increment base updates:
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VST1_UPD,
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VST2_UPD,
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VST3_UPD,
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VST4_UPD,
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VST2LN_UPD,
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VST3LN_UPD,
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VST4LN_UPD,
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// Load/Store of dual registers
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LDRD,
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STRD
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};
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} // end namespace ARMISD
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/// Define some predicates that are used for node matching.
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namespace ARM {
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bool isBitFieldInvertedMask(unsigned v);
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} // end namespace ARM
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//===--------------------------------------------------------------------===//
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// ARMTargetLowering - ARM Implementation of the TargetLowering interface
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class ARMTargetLowering : public TargetLowering {
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public:
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explicit ARMTargetLowering(const TargetMachine &TM,
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const ARMSubtarget &STI);
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unsigned getJumpTableEncoding() const override;
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bool useSoftFloat() const override;
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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/// ReplaceNodeResults - Replace the results of node with an illegal result
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/// type with new values built out of custom code.
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void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
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SelectionDAG &DAG) const override;
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const char *getTargetNodeName(unsigned Opcode) const override;
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bool isSelectSupported(SelectSupportKind Kind) const override {
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// ARM does not support scalar condition selects on vectors.
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return (Kind != ScalarCondVectorVal);
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}
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bool isReadOnly(const GlobalValue *GV) const;
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/// getSetCCResultType - Return the value type to use for ISD::SETCC.
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EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
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EVT VT) const override;
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *MBB) const override;
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void AdjustInstrPostInstrSelection(MachineInstr &MI,
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SDNode *Node) const override;
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SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
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SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
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SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
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SDValue PerformIntrinsicCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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bool SimplifyDemandedBitsForTargetNode(SDValue Op,
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const APInt &OriginalDemandedBits,
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const APInt &OriginalDemandedElts,
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KnownBits &Known,
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TargetLoweringOpt &TLO,
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unsigned Depth) const override;
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bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
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/// allowsMisalignedMemoryAccesses - Returns true if the target allows
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/// unaligned memory accesses of the specified type. Returns whether it
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/// is "fast" by reference in the second argument.
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bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
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unsigned Align,
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MachineMemOperand::Flags Flags,
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bool *Fast) const override;
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EVT getOptimalMemOpType(const MemOp &Op,
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const AttributeList &FuncAttributes) const override;
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bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
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bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
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bool isZExtFree(SDValue Val, EVT VT2) const override;
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bool shouldSinkOperands(Instruction *I,
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SmallVectorImpl<Use *> &Ops) const override;
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Type* shouldConvertSplatType(ShuffleVectorInst* SVI) const override;
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bool isFNegFree(EVT VT) const override;
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bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
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bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
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/// isLegalAddressingMode - Return true if the addressing mode represented
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/// by AM is legal for this target, for a load/store of the specified type.
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bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
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Type *Ty, unsigned AS,
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Instruction *I = nullptr) const override;
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/// getScalingFactorCost - Return the cost of the scaling used in
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/// addressing mode represented by AM.
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/// If the AM is supported, the return value must be >= 0.
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/// If the AM is not supported, the return value must be negative.
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int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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unsigned AS) const override;
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bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
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/// Returns true if the addressing mode representing by AM is legal
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/// for the Thumb1 target, for a load/store of the specified type.
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bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
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/// isLegalICmpImmediate - Return true if the specified immediate is legal
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/// icmp immediate, that is the target has icmp instructions which can
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/// compare a register against the immediate without having to materialize
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/// the immediate into a register.
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bool isLegalICmpImmediate(int64_t Imm) const override;
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/// isLegalAddImmediate - Return true if the specified immediate is legal
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/// add immediate, that is the target has add instructions which can
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/// add a register and the immediate without having to materialize
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/// the immediate into a register.
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bool isLegalAddImmediate(int64_t Imm) const override;
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/// getPreIndexedAddressParts - returns true by value, base pointer and
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/// offset pointer and addressing mode by reference if the node's address
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/// can be legally represented as pre-indexed load / store address.
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bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
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ISD::MemIndexedMode &AM,
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SelectionDAG &DAG) const override;
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/// getPostIndexedAddressParts - returns true by value, base pointer and
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/// offset pointer and addressing mode by reference if this node can be
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/// combined with a load / store to form a post-indexed load / store.
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bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
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SDValue &Offset, ISD::MemIndexedMode &AM,
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SelectionDAG &DAG) const override;
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void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
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const APInt &DemandedElts,
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const SelectionDAG &DAG,
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unsigned Depth) const override;
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bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
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const APInt &DemandedElts,
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TargetLoweringOpt &TLO) const override;
|
|
|
|
bool ExpandInlineAsm(CallInst *CI) const override;
|
|
|
|
ConstraintType getConstraintType(StringRef Constraint) const override;
|
|
|
|
/// Examine constraint string and operand type and determine a weight value.
|
|
/// The operand object must already have been set up with the operand type.
|
|
ConstraintWeight getSingleConstraintMatchWeight(
|
|
AsmOperandInfo &info, const char *constraint) const override;
|
|
|
|
std::pair<unsigned, const TargetRegisterClass *>
|
|
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
|
|
StringRef Constraint, MVT VT) const override;
|
|
|
|
const char *LowerXConstraint(EVT ConstraintVT) const override;
|
|
|
|
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
|
|
/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
|
|
/// true it means one of the asm constraint of the inline asm instruction
|
|
/// being processed is 'm'.
|
|
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
|
|
std::vector<SDValue> &Ops,
|
|
SelectionDAG &DAG) const override;
|
|
|
|
unsigned
|
|
getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
|
|
if (ConstraintCode == "Q")
|
|
return InlineAsm::Constraint_Q;
|
|
else if (ConstraintCode == "o")
|
|
return InlineAsm::Constraint_o;
|
|
else if (ConstraintCode.size() == 2) {
|
|
if (ConstraintCode[0] == 'U') {
|
|
switch(ConstraintCode[1]) {
|
|
default:
|
|
break;
|
|
case 'm':
|
|
return InlineAsm::Constraint_Um;
|
|
case 'n':
|
|
return InlineAsm::Constraint_Un;
|
|
case 'q':
|
|
return InlineAsm::Constraint_Uq;
|
|
case 's':
|
|
return InlineAsm::Constraint_Us;
|
|
case 't':
|
|
return InlineAsm::Constraint_Ut;
|
|
case 'v':
|
|
return InlineAsm::Constraint_Uv;
|
|
case 'y':
|
|
return InlineAsm::Constraint_Uy;
|
|
}
|
|
}
|
|
}
|
|
return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
|
|
}
|
|
|
|
const ARMSubtarget* getSubtarget() const {
|
|
return Subtarget;
|
|
}
|
|
|
|
/// getRegClassFor - Return the register class that should be used for the
|
|
/// specified value type.
|
|
const TargetRegisterClass *
|
|
getRegClassFor(MVT VT, bool isDivergent = false) const override;
|
|
|
|
bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
|
|
unsigned &PrefAlign) const override;
|
|
|
|
/// createFastISel - This method returns a target specific FastISel object,
|
|
/// or null if the target does not support "fast" ISel.
|
|
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
|
|
const TargetLibraryInfo *libInfo) const override;
|
|
|
|
Sched::Preference getSchedulingPreference(SDNode *N) const override;
|
|
|
|
bool
|
|
isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
|
|
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
|
|
|
|
/// isFPImmLegal - Returns true if the target can instruction select the
|
|
/// specified FP immediate natively. If false, the legalizer will
|
|
/// materialize the FP immediate as a load from a constant pool.
|
|
bool isFPImmLegal(const APFloat &Imm, EVT VT,
|
|
bool ForCodeSize = false) const override;
|
|
|
|
bool getTgtMemIntrinsic(IntrinsicInfo &Info,
|
|
const CallInst &I,
|
|
MachineFunction &MF,
|
|
unsigned Intrinsic) const override;
|
|
|
|
/// Returns true if it is beneficial to convert a load of a constant
|
|
/// to just the constant itself.
|
|
bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
|
|
Type *Ty) const override;
|
|
|
|
/// Return true if EXTRACT_SUBVECTOR is cheap for this result type
|
|
/// with this index.
|
|
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
|
|
unsigned Index) const override;
|
|
|
|
bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
|
|
bool MathUsed) const override {
|
|
// Using overflow ops for overflow checks only should beneficial on ARM.
|
|
return TargetLowering::shouldFormOverflowOp(Opcode, VT, true);
|
|
}
|
|
|
|
/// Returns true if an argument of type Ty needs to be passed in a
|
|
/// contiguous block of registers in calling convention CallConv.
|
|
bool functionArgumentNeedsConsecutiveRegisters(
|
|
Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
|
|
|
|
/// If a physical register, this returns the register that receives the
|
|
/// exception address on entry to an EH pad.
|
|
Register
|
|
getExceptionPointerRegister(const Constant *PersonalityFn) const override;
|
|
|
|
/// If a physical register, this returns the register that receives the
|
|
/// exception typeid on entry to a landing pad.
|
|
Register
|
|
getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
|
|
|
|
Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
|
|
Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
|
|
AtomicOrdering Ord) const override;
|
|
Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
|
|
Value *Addr, AtomicOrdering Ord) const override;
|
|
|
|
void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
|
|
|
|
Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
|
|
AtomicOrdering Ord) const override;
|
|
Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
|
|
AtomicOrdering Ord) const override;
|
|
|
|
unsigned getMaxSupportedInterleaveFactor() const override;
|
|
|
|
bool lowerInterleavedLoad(LoadInst *LI,
|
|
ArrayRef<ShuffleVectorInst *> Shuffles,
|
|
ArrayRef<unsigned> Indices,
|
|
unsigned Factor) const override;
|
|
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
|
|
unsigned Factor) const override;
|
|
|
|
bool shouldInsertFencesForAtomic(const Instruction *I) const override;
|
|
TargetLoweringBase::AtomicExpansionKind
|
|
shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
|
|
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
|
|
TargetLoweringBase::AtomicExpansionKind
|
|
shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
|
|
TargetLoweringBase::AtomicExpansionKind
|
|
shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
|
|
|
|
bool useLoadStackGuardNode() const override;
|
|
|
|
void insertSSPDeclarations(Module &M) const override;
|
|
Value *getSDagStackGuard(const Module &M) const override;
|
|
Function *getSSPStackGuardCheck(const Module &M) const override;
|
|
|
|
bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
|
|
unsigned &Cost) const override;
|
|
|
|
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
|
|
const SelectionDAG &DAG) const override {
|
|
// Do not merge to larger than i32.
|
|
return (MemVT.getSizeInBits() <= 32);
|
|
}
|
|
|
|
bool isCheapToSpeculateCttz() const override;
|
|
bool isCheapToSpeculateCtlz() const override;
|
|
|
|
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
|
|
return VT.isScalarInteger();
|
|
}
|
|
|
|
bool supportSwiftError() const override {
|
|
return true;
|
|
}
|
|
|
|
bool hasStandaloneRem(EVT VT) const override {
|
|
return HasStandaloneRem;
|
|
}
|
|
|
|
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override;
|
|
|
|
CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
|
|
CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
|
|
|
|
/// Returns true if \p VecTy is a legal interleaved access type. This
|
|
/// function checks the vector element type and the overall width of the
|
|
/// vector.
|
|
bool isLegalInterleavedAccessType(unsigned Factor, FixedVectorType *VecTy,
|
|
const DataLayout &DL) const;
|
|
|
|
bool alignLoopsWithOptSize() const override;
|
|
|
|
/// Returns the number of interleaved accesses that will be generated when
|
|
/// lowering accesses of the given type.
|
|
unsigned getNumInterleavedAccesses(VectorType *VecTy,
|
|
const DataLayout &DL) const;
|
|
|
|
void finalizeLowering(MachineFunction &MF) const override;
|
|
|
|
/// Return the correct alignment for the current calling convention.
|
|
Align getABIAlignmentForCallingConv(Type *ArgTy,
|
|
DataLayout DL) const override;
|
|
|
|
bool isDesirableToCommuteWithShift(const SDNode *N,
|
|
CombineLevel Level) const override;
|
|
|
|
bool shouldFoldConstantShiftPairToMask(const SDNode *N,
|
|
CombineLevel Level) const override;
|
|
|
|
bool preferIncOfAddToSubOfNot(EVT VT) const override;
|
|
|
|
protected:
|
|
std::pair<const TargetRegisterClass *, uint8_t>
|
|
findRepresentativeClass(const TargetRegisterInfo *TRI,
|
|
MVT VT) const override;
|
|
|
|
private:
|
|
/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
|
|
/// make the right decision when generating code for different targets.
|
|
const ARMSubtarget *Subtarget;
|
|
|
|
const TargetRegisterInfo *RegInfo;
|
|
|
|
const InstrItineraryData *Itins;
|
|
|
|
/// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
|
|
unsigned ARMPCLabelIndex;
|
|
|
|
// TODO: remove this, and have shouldInsertFencesForAtomic do the proper
|
|
// check.
|
|
bool InsertFencesForAtomic;
|
|
|
|
bool HasStandaloneRem = true;
|
|
|
|
void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
|
|
void addDRTypeForNEON(MVT VT);
|
|
void addQRTypeForNEON(MVT VT);
|
|
std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
|
|
|
|
using RegsToPassVector = SmallVector<std::pair<unsigned, SDValue>, 8>;
|
|
|
|
void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
|
|
SDValue &Arg, RegsToPassVector &RegsToPass,
|
|
CCValAssign &VA, CCValAssign &NextVA,
|
|
SDValue &StackPtr,
|
|
SmallVectorImpl<SDValue> &MemOpChains,
|
|
ISD::ArgFlagsTy Flags) const;
|
|
SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
|
|
SDValue &Root, SelectionDAG &DAG,
|
|
const SDLoc &dl) const;
|
|
|
|
CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
|
|
bool isVarArg) const;
|
|
CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
|
|
bool isVarArg) const;
|
|
SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
|
|
const SDLoc &dl, SelectionDAG &DAG,
|
|
const CCValAssign &VA,
|
|
ISD::ArgFlagsTy Flags) const;
|
|
SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG,
|
|
const ARMSubtarget *Subtarget) const;
|
|
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
|
|
const ARMSubtarget *Subtarget) const;
|
|
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
|
|
SelectionDAG &DAG) const;
|
|
SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
|
|
SelectionDAG &DAG,
|
|
TLSModel::Model model) const;
|
|
SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
|
|
const ARMSubtarget *ST) const;
|
|
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
|
|
const ARMSubtarget *ST) const;
|
|
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
|
|
void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
|
|
SmallVectorImpl<SDValue> &Results) const;
|
|
SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG,
|
|
const ARMSubtarget *Subtarget) const;
|
|
SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
|
|
SDValue &Chain) const;
|
|
SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
|
|
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFSETCC(SDValue Op, SelectionDAG &DAG) const;
|
|
void lowerABS(SDNode *N, SmallVectorImpl<SDValue> &Results,
|
|
SelectionDAG &DAG) const;
|
|
void LowerLOAD(SDNode *N, SmallVectorImpl<SDValue> &Results,
|
|
SelectionDAG &DAG) const;
|
|
|
|
Register getRegisterByName(const char* RegName, LLT VT,
|
|
const MachineFunction &MF) const override;
|
|
|
|
SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDNode *> &Created) const override;
|
|
|
|
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
|
|
EVT VT) const override;
|
|
|
|
SDValue MoveToHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT, MVT ValVT,
|
|
SDValue Val) const;
|
|
SDValue MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT,
|
|
MVT ValVT, SDValue Val) const;
|
|
|
|
SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
const SDLoc &dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
|
|
SDValue ThisVal) const;
|
|
|
|
bool supportSplitCSR(MachineFunction *MF) const override {
|
|
return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
|
|
MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
|
|
}
|
|
|
|
void initializeSplitCSR(MachineBasicBlock *Entry) const override;
|
|
void insertCopiesSplitCSR(
|
|
MachineBasicBlock *Entry,
|
|
const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
|
|
|
|
bool
|
|
splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
|
|
SDValue *Parts, unsigned NumParts, MVT PartVT,
|
|
Optional<CallingConv::ID> CC) const override;
|
|
|
|
SDValue
|
|
joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL,
|
|
const SDValue *Parts, unsigned NumParts,
|
|
MVT PartVT, EVT ValueVT,
|
|
Optional<CallingConv::ID> CC) const override;
|
|
|
|
SDValue
|
|
LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
const SDLoc &dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const override;
|
|
|
|
int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
|
|
SDValue &Chain, const Value *OrigArg,
|
|
unsigned InRegsParamRecordIdx, int ArgOffset,
|
|
unsigned ArgSize) const;
|
|
|
|
void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
|
|
const SDLoc &dl, SDValue &Chain,
|
|
unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
|
|
bool ForceMutable = false) const;
|
|
|
|
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|
SmallVectorImpl<SDValue> &InVals) const override;
|
|
|
|
/// HandleByVal - Target-specific cleanup for ByVal support.
|
|
void HandleByVal(CCState *, unsigned &, Align) const override;
|
|
|
|
/// IsEligibleForTailCallOptimization - Check whether the call is eligible
|
|
/// for tail call optimization. Targets which want to do tail call
|
|
/// optimization should implement this function.
|
|
bool IsEligibleForTailCallOptimization(
|
|
SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
|
|
bool isCalleeStructRet, bool isCallerStructRet,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG,
|
|
const bool isIndirect) const;
|
|
|
|
bool CanLowerReturn(CallingConv::ID CallConv,
|
|
MachineFunction &MF, bool isVarArg,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
LLVMContext &Context) const override;
|
|
|
|
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
const SDLoc &dl, SelectionDAG &DAG) const override;
|
|
|
|
bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
|
|
|
|
bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
|
|
|
|
bool shouldConsiderGEPOffsetSplit() const override { return true; }
|
|
|
|
bool isUnsupportedFloatingType(EVT VT) const;
|
|
|
|
SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
|
|
SDValue ARMcc, SDValue CCR, SDValue Cmp,
|
|
SelectionDAG &DAG) const;
|
|
SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
|
|
SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
|
|
SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
|
|
const SDLoc &dl, bool Signaling = false) const;
|
|
SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
|
|
|
|
SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
|
|
MachineBasicBlock *DispatchBB, int FI) const;
|
|
|
|
void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
|
|
|
|
bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
|
|
|
|
MachineBasicBlock *EmitStructByval(MachineInstr &MI,
|
|
MachineBasicBlock *MBB) const;
|
|
|
|
MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
|
|
MachineBasicBlock *MBB) const;
|
|
MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
|
|
MachineBasicBlock *MBB) const;
|
|
void addMVEVectorTypes(bool HasMVEFP);
|
|
void addAllExtLoads(const MVT From, const MVT To, LegalizeAction Action);
|
|
void setAllExpand(MVT VT);
|
|
};
|
|
|
|
enum VMOVModImmType {
|
|
VMOVModImm,
|
|
VMVNModImm,
|
|
MVEVMVNModImm,
|
|
OtherModImm
|
|
};
|
|
|
|
namespace ARM {
|
|
|
|
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
|
|
const TargetLibraryInfo *libInfo);
|
|
|
|
} // end namespace ARM
|
|
|
|
} // end namespace llvm
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|
|
|
#endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
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