441 lines
12 KiB
TableGen
441 lines
12 KiB
TableGen
//===-- MSP430InstrFormats.td - MSP430 Instruction Formats -*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Describe MSP430 instructions format here
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//
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class SourceMode<bits<2> val> {
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bits<2> Value = val;
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}
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def SrcReg : SourceMode<0>; // r
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def SrcMem : SourceMode<1>; // m
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def SrcIndReg : SourceMode<2>; // n
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def SrcPostInc : SourceMode<3>; // p
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def SrcImm : SourceMode<3>; // i
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// SrcCGImm : SourceMode< >; // c
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class DestMode<bit val> {
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bit Value = val;
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}
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def DstReg : DestMode<0>; // r
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def DstMem : DestMode<1>; // m
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// Generic MSP430 Format
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class MSP430Inst<dag outs, dag ins, int size, string asmstr> : Instruction {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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let Namespace = "MSP430";
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = asmstr;
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let Size = size;
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}
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// MSP430 Double Operand (Format I) Instructions
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class IForm<bits<4> opcode, DestMode ad, bit bw, SourceMode as, int size,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: MSP430Inst<outs, ins, size, asmstr> {
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let Pattern = pattern;
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bits<4> rs;
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bits<4> rd;
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let Inst{15-12} = opcode;
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let Inst{11-8} = rs;
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let Inst{7} = ad.Value;
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let Inst{6} = bw;
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let Inst{5-4} = as.Value;
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let Inst{3-0} = rd;
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}
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// 8 bit IForm instructions
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class IForm8<bits<4> opcode, DestMode dest, SourceMode src, int size,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IForm<opcode, dest, 1, src, size, outs, ins, asmstr, pattern>;
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class I8rr<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IForm8<opcode, DstReg, SrcReg, 2, outs, ins, asmstr, pattern> {
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let DecoderNamespace = "Alpha";
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}
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class I8ri<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IForm8<opcode, DstReg, SrcImm, 4, outs, ins, asmstr, pattern> {
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let DecoderNamespace = "Gamma";
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bits<16> imm;
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let Inst{31-16} = imm;
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let rs = 0b0000;
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}
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class I8rc<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: MSP430Inst<outs, ins, 2, asmstr> {
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let DecoderNamespace = "Beta";
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let Pattern = pattern;
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bits<6> imm;
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bits<4> rd;
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let Inst{15-12} = opcode;
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let Inst{11-8} = imm{3-0};
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let Inst{7} = DstReg.Value;
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let Inst{6} = 1;
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let Inst{5-4} = imm{5-4};
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let Inst{3-0} = rd;
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}
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class I8rm<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IForm8<opcode, DstReg, SrcMem, 4, outs, ins, asmstr, pattern> {
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let DecoderNamespace = "Gamma";
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bits<20> src;
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let rs = src{3-0};
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let Inst{31-16} = src{19-4};
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}
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class I8rn<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IForm8<opcode, DstReg, SrcIndReg, 2, outs, ins, asmstr, pattern> {
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let DecoderNamespace = "Delta";
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}
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class I8rp<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IForm8<opcode, DstReg, SrcPostInc, 2, outs, ins, asmstr, pattern> {
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let DecoderNamespace = "Delta";
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}
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class I8mr<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IForm8<opcode, DstMem, SrcReg, 4, outs, ins, asmstr, pattern> {
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let DecoderNamespace = "Alpha";
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bits<20> dst;
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let rd = dst{3-0};
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let Inst{31-16} = dst{19-4};
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}
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class I8mi<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IForm8<opcode, DstMem, SrcImm, 6, outs, ins, asmstr, pattern> {
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let DecoderNamespace = "Gamma";
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bits<16> imm;
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bits<20> dst;
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let rs = 0b0000;
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let Inst{31-16} = imm;
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let rd = dst{3-0};
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let Inst{47-32} = dst{19-4};
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}
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class I8mc<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: MSP430Inst<outs, ins, 4, asmstr> {
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let DecoderNamespace = "Beta";
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let Pattern = pattern;
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bits<6> imm;
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bits<20> dst;
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let Inst{31-16} = dst{19-4};
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let Inst{15-12} = opcode;
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let Inst{11-8} = imm{3-0};
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let Inst{7} = DstMem.Value;
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let Inst{6} = 1;
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let Inst{5-4} = imm{5-4};
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let Inst{3-0} = dst{3-0};
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}
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class I8mm<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IForm8<opcode, DstMem, SrcMem, 6, outs, ins, asmstr, pattern> {
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let DecoderNamespace = "Gamma";
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bits<20> src;
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bits<20> dst;
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let rs = src{3-0};
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let Inst{31-16} = src{19-4};
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let rd = dst{3-0};
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let Inst{47-32} = dst{19-4};
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}
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class I8mn<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IForm8<opcode, DstMem, SrcIndReg, 4, outs, ins, asmstr, pattern> {
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let DecoderNamespace = "Delta";
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bits<20> dst;
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let rd = dst{3-0};
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let Inst{31-16} = dst{19-4};
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}
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class I8mp<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IForm8<opcode, DstMem, SrcPostInc, 4, outs, ins, asmstr, pattern> {
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let DecoderNamespace = "Delta";
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bits<20> dst;
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let rd = dst{3-0};
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let Inst{31-16} = dst{19-4};
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}
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// 16 bit IForm instructions
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class IForm16<bits<4> opcode, DestMode dest, SourceMode src, int size,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IForm<opcode, dest, 0, src, size, outs, ins, asmstr, pattern>;
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class I16rr<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IForm16<opcode, DstReg, SrcReg, 2, outs, ins, asmstr, pattern> {
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let DecoderNamespace = "Alpha";
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}
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class I16ri<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IForm16<opcode, DstReg, SrcImm, 4, outs, ins, asmstr, pattern> {
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let DecoderNamespace = "Gamma";
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bits<16> imm;
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let Inst{31-16} = imm;
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let rs = 0b0000;
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}
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class I16rc<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: MSP430Inst<outs, ins, 2, asmstr> {
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let DecoderNamespace = "Beta";
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let Pattern = pattern;
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bits<6> imm;
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bits<4> rd;
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let Inst{15-12} = opcode;
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let Inst{11-8} = imm{3-0};
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let Inst{7} = DstReg.Value;
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let Inst{6} = 0;
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let Inst{5-4} = imm{5-4};
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let Inst{3-0} = rd;
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}
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class I16rm<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IForm16<opcode, DstReg, SrcMem, 4, outs, ins, asmstr, pattern> {
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let DecoderNamespace = "Gamma";
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bits<20> src;
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let rs = src{3-0};
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let Inst{31-16} = src{19-4};
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}
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class I16rn<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IForm16<opcode, DstReg, SrcIndReg, 2, outs, ins, asmstr, pattern> {
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let DecoderNamespace = "Delta";
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}
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class I16rp<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IForm16<opcode, DstReg, SrcPostInc, 2, outs, ins, asmstr, pattern> {
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let DecoderNamespace = "Delta";
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}
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class I16mr<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IForm16<opcode, DstMem, SrcReg, 4, outs, ins, asmstr, pattern> {
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let DecoderNamespace = "Alpha";
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bits<20> dst;
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let rd = dst{3-0};
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let Inst{31-16} = dst{19-4};
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}
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class I16mi<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IForm16<opcode, DstMem, SrcImm, 6, outs, ins, asmstr, pattern> {
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let DecoderNamespace = "Gamma";
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bits<16> imm;
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bits<20> dst;
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let Inst{31-16} = imm;
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let rs = 0b0000;
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let rd = dst{3-0};
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let Inst{47-32} = dst{19-4};
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}
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class I16mc<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: MSP430Inst<outs, ins, 4, asmstr> {
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let DecoderNamespace = "Beta";
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let Pattern = pattern;
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bits<6> imm;
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bits<20> dst;
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let Inst{31-16} = dst{19-4};
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let Inst{15-12} = opcode;
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let Inst{11-8} = imm{3-0};
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let Inst{7} = DstMem.Value;
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let Inst{6} = 0;
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let Inst{5-4} = imm{5-4};
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let Inst{3-0} = dst{3-0};
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}
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class I16mm<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IForm16<opcode, DstMem, SrcMem, 6, outs, ins, asmstr, pattern> {
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let DecoderNamespace = "Gamma";
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bits<20> src;
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bits<20> dst;
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let rs = src{3-0};
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let Inst{31-16} = src{19-4};
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let rd = dst{3-0};
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let Inst{47-32} = dst{19-4};
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}
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class I16mn<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IForm16<opcode, DstMem, SrcIndReg, 4, outs, ins, asmstr, pattern> {
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let DecoderNamespace = "Delta";
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bits<20> dst;
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let rd = dst{3-0};
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let Inst{31-16} = dst{19-4};
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}
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class I16mp<bits<4> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IForm16<opcode, DstMem, SrcPostInc, 4, outs, ins, asmstr, pattern> {
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let DecoderNamespace = "Delta";
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bits<20> dst;
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let rd = dst{3-0};
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let Inst{31-16} = dst{19-4};
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}
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// MSP430 Single Operand (Format II) Instructions
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class IIForm<bits<3> opcode, bit bw, SourceMode as, int size,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: MSP430Inst<outs, ins, size, asmstr> {
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let Pattern = pattern;
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bits<4> rs;
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let Inst{15-10} = 0b000100;
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let Inst{9-7} = opcode;
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let Inst{6} = bw;
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let Inst{5-4} = as.Value;
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let Inst{3-0} = rs;
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}
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// 8 bit IIForm instructions
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class IIForm8<bits<3> opcode, SourceMode src, int size,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IIForm<opcode, 1, src, size, outs, ins, asmstr, pattern>;
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class II8r<bits<3> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IIForm8<opcode, SrcReg, 2, outs, ins, asmstr, pattern>;
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class II8m<bits<3> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IIForm8<opcode, SrcMem, 4, outs, ins, asmstr, pattern> {
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bits<20> src;
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let rs = src{3-0};
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let Inst{31-16} = src{19-4};
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}
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class II8i<bits<3> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IIForm8<opcode, SrcImm, 4, outs, ins, asmstr, pattern> {
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bits<16> imm;
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let rs = 0b0000;
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let Inst{31-16} = imm;
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}
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class II8c<bits<3> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: MSP430Inst<outs, ins, 2, asmstr> {
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let Pattern = pattern;
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bits<6> imm;
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let Inst{15-10} = 0b000100;
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let Inst{9-7} = opcode;
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let Inst{6} = 1;
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let Inst{5-0} = imm;
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}
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class II8n<bits<3> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IIForm8<opcode, SrcIndReg, 2, outs, ins, asmstr, pattern>;
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class II8p<bits<3> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IIForm8<opcode, SrcPostInc, 2, outs, ins, asmstr, pattern>;
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// 16 bit IIForm instructions
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class IIForm16<bits<3> opcode, SourceMode src, int size,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IIForm<opcode, 0, src, size, outs, ins, asmstr, pattern>;
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class II16r<bits<3> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IIForm16<opcode, SrcReg, 2, outs, ins, asmstr, pattern>;
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class II16m<bits<3> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IIForm16<opcode, SrcMem, 4, outs, ins, asmstr, pattern> {
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bits<20> src;
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let rs = src{3-0};
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let Inst{31-16} = src{19-4};
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}
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class II16i<bits<3> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IIForm16<opcode, SrcImm, 4, outs, ins, asmstr, pattern> {
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bits<16> imm;
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let rs = 0b0000;
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let Inst{31-16} = imm;
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}
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class II16c<bits<3> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: MSP430Inst<outs, ins, 2, asmstr> {
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let Pattern = pattern;
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bits<6> imm;
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let Inst{15-10} = 0b000100;
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let Inst{9-7} = opcode;
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let Inst{6} = 0;
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let Inst{5-0} = imm;
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}
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class II16n<bits<3> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IIForm16<opcode, SrcIndReg, 2, outs, ins, asmstr, pattern>;
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class II16p<bits<3> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: IIForm16<opcode, SrcPostInc, 2, outs, ins, asmstr, pattern>;
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// MSP430 Conditional Jumps Instructions
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class CJForm<dag outs, dag ins, string asmstr, list<dag> pattern>
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: MSP430Inst<outs, ins, 2, asmstr> {
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let Pattern = pattern;
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bits<3> cond;
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bits<10> dst;
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let Inst{15-13} = 0b001;
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let Inst{12-10} = cond;
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let Inst{9-0} = dst;
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}
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// Pseudo instructions
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class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
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: MSP430Inst<outs, ins, 0, asmstr> {
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let Pattern = pattern;
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}
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