40 lines
1.1 KiB
YAML
40 lines
1.1 KiB
YAML
# RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs -run-pass=aarch64-ldst-opt %s -o - | FileCheck %s
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#
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# The test below tests that when the AArch64 Load Store Optimization pass tries to
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# convert load instructions into a ldp instruction, and when the destination
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# registers are sub/super register of each other, then the convertion should not occur.
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#
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# For example, for the following pattern:
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# ldr x10 [x9]
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# ldr w10 [x9, 8],
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# We cannot convert it to an ldp instruction.
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#
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# CHECK-NOT: LDP
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# CHECK: $x10 = LDRSWui $x9, 0
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# CHECK: $w10 = LDRWui $x9, 1
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# CHECK: RET
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---
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name: test1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x9
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$x10 = LDRSWui $x9, 0 :: (load 4)
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$w10 = LDRWui $x9, 1 :: (load 4)
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RET undef $lr, implicit undef $w0
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...
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# CHECK-NOT: LDP
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# CHECK: $w10 = LDRWui $x9, 0
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# CHECK: $x10 = LDRSWui $x9, 1
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# CHECK: RET
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---
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name: test2
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x9
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$w10 = LDRWui $x9, 0 :: (load 4)
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$x10 = LDRSWui $x9, 1 :: (load 4)
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RET undef $lr, implicit undef $w0
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...
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