353 lines
18 KiB
LLVM
353 lines
18 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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;
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; LD1B, LD1W, LD1H, LD1D: base + 32-bit unscaled offset, sign (sxtw) or zero
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; (uxtw) extended to 64 bits.
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; e.g. ld1h { z0.d }, p0/z, [x0, z0.d, uxtw]
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;
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; LD1B
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define <vscale x 4 x i32> @gld1b_s_uxtw(<vscale x 4 x i1> %pg, i8* %base, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: gld1b_s_uxtw:
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; CHECK: ld1b { z0.s }, p0/z, [x0, z0.s, uxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i8(<vscale x 4 x i1> %pg,
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i8* %base,
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<vscale x 4 x i32> %b)
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%res = zext <vscale x 4 x i8> %load to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 4 x i32> @gld1b_s_sxtw(<vscale x 4 x i1> %pg, i8* %base, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: gld1b_s_sxtw:
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; CHECK: ld1b { z0.s }, p0/z, [x0, z0.s, sxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i8(<vscale x 4 x i1> %pg,
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i8* %base,
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<vscale x 4 x i32> %b)
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%res = zext <vscale x 4 x i8> %load to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @gld1b_d_uxtw(<vscale x 2 x i1> %pg, i8* %base, <vscale x 2 x i32> %b) {
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; CHECK-LABEL: gld1b_d_uxtw:
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; CHECK: ld1b { z0.d }, p0/z, [x0, z0.d, uxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i8(<vscale x 2 x i1> %pg,
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i8* %base,
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<vscale x 2 x i32> %b)
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%res = zext <vscale x 2 x i8> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 2 x i64> @gld1b_d_sxtw(<vscale x 2 x i1> %pg, i8* %base, <vscale x 2 x i32> %b) {
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; CHECK-LABEL: gld1b_d_sxtw:
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; CHECK: ld1b { z0.d }, p0/z, [x0, z0.d, sxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i8(<vscale x 2 x i1> %pg,
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i8* %base,
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<vscale x 2 x i32> %b)
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%res = zext <vscale x 2 x i8> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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; LD1H
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define <vscale x 4 x i32> @gld1h_s_uxtw(<vscale x 4 x i1> %pg, i16* %base, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: gld1h_s_uxtw:
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; CHECK: ld1h { z0.s }, p0/z, [x0, z0.s, uxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i16(<vscale x 4 x i1> %pg,
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i16* %base,
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<vscale x 4 x i32> %b)
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%res = zext <vscale x 4 x i16> %load to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 4 x i32> @gld1h_s_sxtw(<vscale x 4 x i1> %pg, i16* %base, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: gld1h_s_sxtw:
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; CHECK: ld1h { z0.s }, p0/z, [x0, z0.s, sxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i16(<vscale x 4 x i1> %pg,
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i16* %base,
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<vscale x 4 x i32> %b)
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%res = zext <vscale x 4 x i16> %load to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @gld1h_d_uxtw(<vscale x 2 x i1> %pg, i16* %base, <vscale x 2 x i32> %b) {
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; CHECK-LABEL: gld1h_d_uxtw:
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; CHECK: ld1h { z0.d }, p0/z, [x0, z0.d, uxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i16(<vscale x 2 x i1> %pg,
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i16* %base,
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<vscale x 2 x i32> %b)
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%res = zext <vscale x 2 x i16> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 2 x i64> @gld1h_d_sxtw(<vscale x 2 x i1> %pg, i16* %base, <vscale x 2 x i32> %b) {
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; CHECK-LABEL: gld1h_d_sxtw:
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; CHECK: ld1h { z0.d }, p0/z, [x0, z0.d, sxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i16(<vscale x 2 x i1> %pg,
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i16* %base,
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<vscale x 2 x i32> %b)
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%res = zext <vscale x 2 x i16> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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; LD1W
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define <vscale x 4 x i32> @gld1w_s_uxtw(<vscale x 4 x i1> %pg, i32* %base, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: gld1w_s_uxtw:
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; CHECK: ld1w { z0.s }, p0/z, [x0, z0.s, uxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i32(<vscale x 4 x i1> %pg,
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i32* %base,
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<vscale x 4 x i32> %b)
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ret <vscale x 4 x i32> %load
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}
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define <vscale x 4 x i32> @gld1w_s_sxtw(<vscale x 4 x i1> %pg, i32* %base, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: gld1w_s_sxtw:
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; CHECK: ld1w { z0.s }, p0/z, [x0, z0.s, sxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i32(<vscale x 4 x i1> %pg,
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i32* %base,
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<vscale x 4 x i32> %b)
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ret <vscale x 4 x i32> %load
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}
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define <vscale x 2 x i64> @gld1w_d_uxtw(<vscale x 2 x i1> %pg, i32* %base, <vscale x 2 x i32> %b) {
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; CHECK-LABEL: gld1w_d_uxtw:
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; CHECK: ld1w { z0.d }, p0/z, [x0, z0.d, uxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i32(<vscale x 2 x i1> %pg,
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i32* %base,
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<vscale x 2 x i32> %b)
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%res = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 2 x i64> @gld1w_d_sxtw(<vscale x 2 x i1> %pg, i32* %base, <vscale x 2 x i32> %b) {
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; CHECK-LABEL: gld1w_d_sxtw:
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; CHECK: ld1w { z0.d }, p0/z, [x0, z0.d, sxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i32(<vscale x 2 x i1> %pg,
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i32* %base,
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<vscale x 2 x i32> %b)
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%res = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 4 x float> @gld1w_s_uxtw_float(<vscale x 4 x i1> %pg, float* %base, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: gld1w_s_uxtw_float:
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; CHECK: ld1w { z0.s }, p0/z, [x0, z0.s, uxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x float> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4f32(<vscale x 4 x i1> %pg,
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float* %base,
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<vscale x 4 x i32> %b)
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ret <vscale x 4 x float> %load
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}
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define <vscale x 4 x float> @gld1w_s_sxtw_float(<vscale x 4 x i1> %pg, float* %base, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: gld1w_s_sxtw_float:
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; CHECK: ld1w { z0.s }, p0/z, [x0, z0.s, sxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x float> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4f32(<vscale x 4 x i1> %pg,
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float* %base,
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<vscale x 4 x i32> %b)
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ret <vscale x 4 x float> %load
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}
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; LD1D
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define <vscale x 2 x i64> @gld1d_d_uxtw(<vscale x 2 x i1> %pg, i64* %base, <vscale x 2 x i32> %b) {
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; CHECK-LABEL: gld1d_d_uxtw:
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; CHECK: ld1d { z0.d }, p0/z, [x0, z0.d, uxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i64(<vscale x 2 x i1> %pg,
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i64* %base,
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<vscale x 2 x i32> %b)
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ret <vscale x 2 x i64> %load
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}
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define <vscale x 2 x i64> @gld1d_d_sxtw(<vscale x 2 x i1> %pg, i64* %base, <vscale x 2 x i32> %b) {
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; CHECK-LABEL: gld1d_d_sxtw:
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; CHECK: ld1d { z0.d }, p0/z, [x0, z0.d, sxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i64(<vscale x 2 x i1> %pg,
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i64* %base,
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<vscale x 2 x i32> %b)
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ret <vscale x 2 x i64> %load
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}
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define <vscale x 2 x double> @gld1d_d_uxtw_double(<vscale x 2 x i1> %pg, double* %base, <vscale x 2 x i32> %b) {
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; CHECK-LABEL: gld1d_d_uxtw_double:
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; CHECK: ld1d { z0.d }, p0/z, [x0, z0.d, uxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2f64(<vscale x 2 x i1> %pg,
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double* %base,
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<vscale x 2 x i32> %b)
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ret <vscale x 2 x double> %load
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}
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define <vscale x 2 x double> @gld1d_d_sxtw_double(<vscale x 2 x i1> %pg, double* %base, <vscale x 2 x i32> %b) {
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; CHECK-LABEL: gld1d_d_sxtw_double:
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; CHECK: ld1d { z0.d }, p0/z, [x0, z0.d, sxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2f64(<vscale x 2 x i1> %pg,
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double* %base,
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<vscale x 2 x i32> %b)
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ret <vscale x 2 x double> %load
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}
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;
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; LD1SB, LD1SW, LD1SH: base + 32-bit unscaled offset, sign (sxtw) or zero
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; (uxtw) extended to 64 bits.
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; e.g. ld1sh { z0.d }, p0/z, [x0, z0.d, uxtw]
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;
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; LD1SB
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define <vscale x 4 x i32> @gld1sb_s_uxtw(<vscale x 4 x i1> %pg, i8* %base, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: gld1sb_s_uxtw:
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; CHECK: ld1sb { z0.s }, p0/z, [x0, z0.s, uxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i8(<vscale x 4 x i1> %pg,
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i8* %base,
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<vscale x 4 x i32> %b)
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%res = sext <vscale x 4 x i8> %load to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 4 x i32> @gld1sb_s_sxtw(<vscale x 4 x i1> %pg, i8* %base, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: gld1sb_s_sxtw:
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; CHECK: ld1sb { z0.s }, p0/z, [x0, z0.s, sxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i8(<vscale x 4 x i1> %pg,
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i8* %base,
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<vscale x 4 x i32> %b)
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%res = sext <vscale x 4 x i8> %load to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @gld1sb_d_uxtw(<vscale x 2 x i1> %pg, i8* %base, <vscale x 2 x i32> %b) {
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; CHECK-LABEL: gld1sb_d_uxtw:
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; CHECK: ld1sb { z0.d }, p0/z, [x0, z0.d, uxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i8(<vscale x 2 x i1> %pg,
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i8* %base,
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<vscale x 2 x i32> %b)
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%res = sext <vscale x 2 x i8> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 2 x i64> @gld1sb_d_sxtw(<vscale x 2 x i1> %pg, i8* %base, <vscale x 2 x i32> %b) {
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; CHECK-LABEL: gld1sb_d_sxtw:
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; CHECK: ld1sb { z0.d }, p0/z, [x0, z0.d, sxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i8(<vscale x 2 x i1> %pg,
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i8* %base,
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<vscale x 2 x i32> %b)
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%res = sext <vscale x 2 x i8> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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; LD1SH
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define <vscale x 4 x i32> @gld1sh_s_uxtw(<vscale x 4 x i1> %pg, i16* %base, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: gld1sh_s_uxtw:
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; CHECK: ld1sh { z0.s }, p0/z, [x0, z0.s, uxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i16(<vscale x 4 x i1> %pg,
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i16* %base,
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<vscale x 4 x i32> %b)
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%res = sext <vscale x 4 x i16> %load to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 4 x i32> @gld1sh_s_sxtw(<vscale x 4 x i1> %pg, i16* %base, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: gld1sh_s_sxtw:
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; CHECK: ld1sh { z0.s }, p0/z, [x0, z0.s, sxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i16(<vscale x 4 x i1> %pg,
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i16* %base,
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<vscale x 4 x i32> %b)
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%res = sext <vscale x 4 x i16> %load to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @gld1sh_d_uxtw(<vscale x 2 x i1> %pg, i16* %base, <vscale x 2 x i32> %b) {
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; CHECK-LABEL: gld1sh_d_uxtw:
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; CHECK: ld1sh { z0.d }, p0/z, [x0, z0.d, uxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i16(<vscale x 2 x i1> %pg,
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i16* %base,
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<vscale x 2 x i32> %b)
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%res = sext <vscale x 2 x i16> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 2 x i64> @gld1sh_d_sxtw(<vscale x 2 x i1> %pg, i16* %base, <vscale x 2 x i32> %b) {
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; CHECK-LABEL: gld1sh_d_sxtw:
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; CHECK: ld1sh { z0.d }, p0/z, [x0, z0.d, sxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i16(<vscale x 2 x i1> %pg,
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i16* %base,
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<vscale x 2 x i32> %b)
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%res = sext <vscale x 2 x i16> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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; LD1SW
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define <vscale x 2 x i64> @gld1sw_d_uxtw(<vscale x 2 x i1> %pg, i32* %base, <vscale x 2 x i32> %b) {
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; CHECK-LABEL: gld1sw_d_uxtw:
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; CHECK: ld1sw { z0.d }, p0/z, [x0, z0.d, uxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i32(<vscale x 2 x i1> %pg,
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i32* %base,
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<vscale x 2 x i32> %b)
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%res = sext <vscale x 2 x i32> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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|
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define <vscale x 2 x i64> @gld1sw_d_sxtw(<vscale x 2 x i1> %pg, i32* %base, <vscale x 2 x i32> %b) {
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; CHECK-LABEL: gld1sw_d_sxtw:
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; CHECK: ld1sw { z0.d }, p0/z, [x0, z0.d, sxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i32(<vscale x 2 x i1> %pg,
|
|
i32* %base,
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|
<vscale x 2 x i32> %b)
|
|
%res = sext <vscale x 2 x i32> %load to <vscale x 2 x i64>
|
|
ret <vscale x 2 x i64> %res
|
|
}
|
|
|
|
; LD1B/LD1SB
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declare <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i8(<vscale x 4 x i1>, i8*, <vscale x 4 x i32>)
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declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i8(<vscale x 2 x i1>, i8*, <vscale x 2 x i32>)
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declare <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i8(<vscale x 4 x i1>, i8*, <vscale x 4 x i32>)
|
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declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i8(<vscale x 2 x i1>, i8*, <vscale x 2 x i32>)
|
|
|
|
; LD1H/LD1SH
|
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declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i16(<vscale x 4 x i1>, i16*, <vscale x 4 x i32>)
|
|
declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i16(<vscale x 2 x i1>, i16*, <vscale x 2 x i32>)
|
|
declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i16(<vscale x 4 x i1>, i16*, <vscale x 4 x i32>)
|
|
declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i16(<vscale x 2 x i1>, i16*, <vscale x 2 x i32>)
|
|
|
|
; LD1W/LD1SW
|
|
declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i32(<vscale x 4 x i1>, i32*, <vscale x 4 x i32>)
|
|
declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i32(<vscale x 2 x i1>, i32*, <vscale x 2 x i32>)
|
|
declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i32(<vscale x 4 x i1>, i32*, <vscale x 4 x i32>)
|
|
declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i32(<vscale x 2 x i1>, i32*, <vscale x 2 x i32>)
|
|
|
|
declare <vscale x 4 x float> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4f32(<vscale x 4 x i1>, float*, <vscale x 4 x i32>)
|
|
declare <vscale x 4 x float> @llvm.aarch64.sve.ld1.gather.uxtw.nxv4f32(<vscale x 4 x i1>, float*, <vscale x 4 x i32>)
|
|
|
|
; LD1D
|
|
declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i64(<vscale x 2 x i1>, i64*, <vscale x 2 x i32>)
|
|
declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2i64(<vscale x 2 x i1>, i64*, <vscale x 2 x i32>)
|
|
|
|
declare <vscale x 2 x double> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2f64(<vscale x 2 x i1>, double*, <vscale x 2 x i32>)
|
|
declare <vscale x 2 x double> @llvm.aarch64.sve.ld1.gather.uxtw.nxv2f64(<vscale x 2 x i1>, double*, <vscale x 2 x i32>)
|