113 lines
5.7 KiB
LLVM
113 lines
5.7 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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;
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; SEL (Vectors)
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;
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define <vscale x 16 x i1> @sel_i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
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; CHECK-LABEL: sel_i1:
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; CHECK: sel p0.b, p0, p1.b, p2.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i1> @llvm.aarch64.sve.sel.nxv16i1(<vscale x 16 x i1> %pg,
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<vscale x 16 x i1> %a,
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<vscale x 16 x i1> %b)
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ret <vscale x 16 x i1> %out
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}
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define <vscale x 16 x i8> @sel_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: sel_i8:
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; CHECK: sel z0.b, p0, z0.b, z1.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg,
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<vscale x 16 x i8> %a,
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<vscale x 16 x i8> %b)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @sel_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: sel_i16:
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; CHECK: sel z0.h, p0, z0.h, z1.h
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %pg,
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<vscale x 8 x i16> %a,
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<vscale x 8 x i16> %b)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @sel_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: sel_i32:
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; CHECK: sel z0.s, p0, z0.s, z1.s
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %a,
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<vscale x 4 x i32> %b)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 2 x i64> @sel_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: sel_i64:
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; CHECK: sel z0.d, p0, z0.d, z1.d
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %a,
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<vscale x 2 x i64> %b)
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ret <vscale x 2 x i64> %out
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}
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define <vscale x 8 x bfloat> @sel_bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) #0 {
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; CHECK-LABEL: sel_bf16:
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; CHECK: sel z0.h, p0, z0.h, z1.h
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.sel.nxv8bf16(<vscale x 8 x i1> %pg,
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<vscale x 8 x bfloat> %a,
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<vscale x 8 x bfloat> %b)
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ret <vscale x 8 x bfloat> %out
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}
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define <vscale x 8 x half> @sel_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
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; CHECK-LABEL: sel_f16:
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; CHECK: sel z0.h, p0, z0.h, z1.h
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1> %pg,
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<vscale x 8 x half> %a,
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<vscale x 8 x half> %b)
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ret <vscale x 8 x half> %out
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}
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define <vscale x 4 x float> @sel_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
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; CHECK-LABEL: sel_f32:
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; CHECK: sel z0.s, p0, z0.s, z1.s
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x float> @llvm.aarch64.sve.sel.nxv4f32(<vscale x 4 x i1> %pg,
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<vscale x 4 x float> %a,
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<vscale x 4 x float> %b)
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ret <vscale x 4 x float> %out
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}
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define <vscale x 2 x double> @sel_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
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; CHECK-LABEL: sel_f64:
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; CHECK: sel z0.d, p0, z0.d, z1.d
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x double> @llvm.aarch64.sve.sel.nxv2f64(<vscale x 2 x i1> %pg,
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<vscale x 2 x double> %a,
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<vscale x 2 x double> %b)
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ret <vscale x 2 x double> %out
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}
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declare <vscale x 16 x i1> @llvm.aarch64.sve.sel.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
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declare <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
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declare <vscale x 8 x bfloat> @llvm.aarch64.sve.sel.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
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declare <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
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declare <vscale x 4 x float> @llvm.aarch64.sve.sel.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
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declare <vscale x 2 x double> @llvm.aarch64.sve.sel.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
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; +bf16 is required for the bfloat version.
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attributes #0 = { "target-features"="+sve,+bf16" }
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