llvm-for-llvmta/test/CodeGen/AMDGPU/lo16-32bit-physreg-copy.mir

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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass postrapseudos -amdgpu-fix-16-bit-physreg-copies -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# GCN-LABEL: name: lo16_to_v32
# GCN: $vgpr1 = V_MOV_B32_e32 $vgpr0, implicit $exec
name: lo16_to_v32
tracksRegLiveness: true
body: |
bb.0:
$vgpr0 = IMPLICIT_DEF
$vgpr1_lo16 = COPY $vgpr0
S_ENDPGM 0
...
# GCN-LABEL: name: v32_to_lo16
# GCN: $vgpr1 = V_MOV_B32_e32 $vgpr0, implicit $exec
name: v32_to_lo16
tracksRegLiveness: true
body: |
bb.0:
$vgpr0 = IMPLICIT_DEF
$vgpr1 = COPY $vgpr0_lo16
S_ENDPGM 0
...
# GCN-LABEL: name: samereg
# GCN: $vgpr0 = IMPLICIT_DEF
# GCN-NEXT: BUNDLE
# GCN-NEXT: S_ENDPGM
name: samereg
tracksRegLiveness: true
body: |
bb.0:
$vgpr0 = IMPLICIT_DEF
$vgpr0 = COPY $vgpr0_lo16
S_ENDPGM 0
...