220 lines
6.3 KiB
LLVM
220 lines
6.3 KiB
LLVM
; Test all important variants of the 'ret' instruction.
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;
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; For non-void returns it is necessary to have something to return so we also
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; test constant generation here.
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;
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; We'll test pointer returns in a separate file since the relocation model
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; affects it and it's undesirable to repeat the non-pointer returns for each
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; relocation model.
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; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,NO-MTHC1,NOT-R6
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; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6
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; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6
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; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6
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; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,R6C
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; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
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; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
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; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
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; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
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; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
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; FIXME: for the test ret_double_0x0, the delay slot of jr cannot be filled
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; as mthc1 has unmodeled side effects. This is an artifact of our backend.
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; Force the delay slot filler off to check that the sequence jr $ra; nop is
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; turned into jic 0, $ra.
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; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
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define void @ret_void() {
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; ALL-LABEL: ret_void:
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; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
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; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC
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ret void
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}
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define i8 @ret_i8() {
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; ALL-LABEL: ret_i8:
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; ALL-DAG: addiu $2, $zero, 3
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; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
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ret i8 3
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}
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define i16 @ret_i16_3() {
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; ALL-LABEL: ret_i16_3:
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; ALL-DAG: addiu $2, $zero, 3
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; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
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ret i16 3
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}
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define i16 @ret_i16_256() {
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; ALL-LABEL: ret_i16_256:
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; ALL-DAG: addiu $2, $zero, 256
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; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
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ret i16 256
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}
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define i16 @ret_i16_257() {
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; ALL-LABEL: ret_i16_257:
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; ALL-DAG: addiu $2, $zero, 257
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; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
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ret i16 257
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}
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define i32 @ret_i32_257() {
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; ALL-LABEL: ret_i32_257:
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; ALL-DAG: addiu $2, $zero, 257
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; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
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ret i32 257
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}
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define i32 @ret_i32_65536() {
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; ALL-LABEL: ret_i32_65536:
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; ALL-DAG: lui $2, 1
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; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
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ret i32 65536
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}
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define i32 @ret_i32_65537() {
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; ALL-LABEL: ret_i32_65537:
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; ALL: lui $[[T0:[0-9]+]], 1
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; ALL-DAG: ori $2, $[[T0]], 1
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; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
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ret i32 65537
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}
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define i64 @ret_i64_65537() {
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; ALL-LABEL: ret_i64_65537:
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; ALL: lui $[[T0:[0-9]+]], 1
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; GPR32-DAG: ori $3, $[[T0]], 1
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; GPR32-DAG: addiu $2, $zero, 0
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; GPR64-DAG: ori $2, $[[T0]], 1
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; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
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ret i64 65537
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}
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define i64 @ret_i64_281479271677952() {
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; ALL-LABEL: ret_i64_281479271677952:
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; ALL-DAG: lui $[[T0:[0-9]+]], 1
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; GPR32-DAG: ori $2, $[[T0]], 1
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; GPR32-DAG: addiu $3, $zero, 0
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; GPR64-DAG: daddiu $[[T1:[0-9]+]], $[[T0]], 1
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; GPR64-DAG: dsll $2, $[[T1]], 32
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; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
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ret i64 281479271677952
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}
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define i64 @ret_i64_281479271809026() {
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; ALL-LABEL: ret_i64_281479271809026:
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; GPR32-DAG: lui $[[T0:[0-9]+]], 1
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; GPR32-DAG: lui $[[T1:[0-9]+]], 2
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; GPR32-DAG: ori $2, $[[T0]], 1
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; GPR32-DAG: ori $3, $[[T1]], 2
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; GPR64-DAG: ori $[[T0:[0-9]+]], $zero, 32769
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; GPR64-DAG: dsll $[[T1:[0-9]+]], $[[T0]], 16
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; GPR64-DAG: daddiu $[[T0:[0-9]+]], $[[T0]], -32767
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; GPR64-DAG: dsll $[[T1:[0-9]+]], $[[T0]], 17
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; GPR64-DAG: daddiu $2, $[[T1]], 2
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; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
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ret i64 281479271809026
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}
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define float @ret_float_0x0() {
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; ALL-LABEL: ret_float_0x0:
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; NO-MTHC1-DAG: mtc1 $zero, $f0
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; MTHC1-DAG: mtc1 $zero, $f0
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; DMTC1-DAG: mtc1 $zero, $f0
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; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
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ret float 0x0000000000000000
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}
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define float @ret_float_0x3() {
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; ALL-LABEL: ret_float_0x3:
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; Use a constant pool
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; O32-DAG: lwc1 $f0, %lo($CPI
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; N64-DAG: lwc1 $f0, %got_ofst($CPI
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; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
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; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC
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; float constants are written as double constants
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ret float 0x36b8000000000000
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}
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define double @ret_double_0x0() {
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; ALL-LABEL: ret_double_0x0:
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; NO-MTHC1-DAG: mtc1 $zero, $f0
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; NO-MTHC1-DAG: mtc1 $zero, $f1
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; MTHC1-DAG: mtc1 $zero, $f0
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; MTHC1-DAG: mthc1 $zero, $f0
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; DMTC1-DAG: dmtc1 $zero, $f0
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; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
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; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC
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ret double 0x0000000000000000
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}
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define double @ret_double_0x3() {
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; ALL-LABEL: ret_double_0x3:
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; Use a constant pool
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; O32-DAG: ldc1 $f0, %lo($CPI
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; N64-DAG: ldc1 $f0, %got_ofst($CPI
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; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
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; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC
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ret double 0x0000000000000003
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}
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