172 lines
4.7 KiB
LLVM
172 lines
4.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \
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; RUN: -target-abi lp64f < %s | FileCheck %s -check-prefix=RV64IZFH
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; This file exhaustively checks half<->i32 conversions. In general,
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; fcvt.l[u].h can be selected instead of fcvt.w[u].h because poison is
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; generated for an fpto[s|u]i conversion if the result doesn't fit in the
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; target type.
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define i32 @aext_fptosi(half %a) nounwind {
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; RV64IZFH-LABEL: aext_fptosi:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
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; RV64IZFH-NEXT: ret
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%1 = fptosi half %a to i32
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ret i32 %1
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}
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define signext i32 @sext_fptosi(half %a) nounwind {
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; RV64IZFH-LABEL: sext_fptosi:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
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; RV64IZFH-NEXT: ret
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%1 = fptosi half %a to i32
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ret i32 %1
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}
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define zeroext i32 @zext_fptosi(half %a) nounwind {
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; RV64IZFH-LABEL: zext_fptosi:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
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; RV64IZFH-NEXT: slli a0, a0, 32
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; RV64IZFH-NEXT: srli a0, a0, 32
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; RV64IZFH-NEXT: ret
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%1 = fptosi half %a to i32
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ret i32 %1
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}
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define i32 @aext_fptoui(half %a) nounwind {
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; RV64IZFH-LABEL: aext_fptoui:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
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; RV64IZFH-NEXT: ret
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%1 = fptoui half %a to i32
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ret i32 %1
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}
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define signext i32 @sext_fptoui(half %a) nounwind {
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; RV64IZFH-LABEL: sext_fptoui:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
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; RV64IZFH-NEXT: ret
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%1 = fptoui half %a to i32
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ret i32 %1
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}
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define zeroext i32 @zext_fptoui(half %a) nounwind {
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; RV64IZFH-LABEL: zext_fptoui:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
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; RV64IZFH-NEXT: ret
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%1 = fptoui half %a to i32
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ret i32 %1
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}
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define i16 @bcvt_f16_to_aext_i16(half %a, half %b) nounwind {
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; RV64IZFH-LABEL: bcvt_f16_to_aext_i16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1
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; RV64IZFH-NEXT: fmv.x.h a0, ft0
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; RV64IZFH-NEXT: ret
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%1 = fadd half %a, %b
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%2 = bitcast half %1 to i16
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ret i16 %2
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}
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define signext i16 @bcvt_f16_to_sext_i16(half %a, half %b) nounwind {
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; RV64IZFH-LABEL: bcvt_f16_to_sext_i16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1
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; RV64IZFH-NEXT: fmv.x.h a0, ft0
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; RV64IZFH-NEXT: slli a0, a0, 48
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; RV64IZFH-NEXT: srai a0, a0, 48
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; RV64IZFH-NEXT: ret
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%1 = fadd half %a, %b
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%2 = bitcast half %1 to i16
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ret i16 %2
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}
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define zeroext i16 @bcvt_f16_to_zext_i16(half %a, half %b) nounwind {
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; RV64IZFH-LABEL: bcvt_f16_to_zext_i16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1
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; RV64IZFH-NEXT: fmv.x.h a0, ft0
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; RV64IZFH-NEXT: lui a1, 16
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; RV64IZFH-NEXT: addiw a1, a1, -1
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; RV64IZFH-NEXT: and a0, a0, a1
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; RV64IZFH-NEXT: ret
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%1 = fadd half %a, %b
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%2 = bitcast half %1 to i16
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ret i16 %2
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}
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define half @bcvt_i64_to_f16_via_i16(i64 %a, i64 %b) nounwind {
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; RV64IZFH-LABEL: bcvt_i64_to_f16_via_i16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmv.h.x ft0, a0
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; RV64IZFH-NEXT: fmv.h.x ft1, a1
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; RV64IZFH-NEXT: fadd.h fa0, ft0, ft1
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; RV64IZFH-NEXT: ret
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%1 = trunc i64 %a to i16
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%2 = trunc i64 %b to i16
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%3 = bitcast i16 %1 to half
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%4 = bitcast i16 %2 to half
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%5 = fadd half %3, %4
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ret half %5
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}
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define half @uitofp_aext_i32_to_f16(i32 %a) nounwind {
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; RV64IZFH-LABEL: uitofp_aext_i32_to_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
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; RV64IZFH-NEXT: ret
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%1 = uitofp i32 %a to half
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ret half %1
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}
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define half @uitofp_sext_i32_to_f16(i32 signext %a) nounwind {
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; RV64IZFH-LABEL: uitofp_sext_i32_to_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
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; RV64IZFH-NEXT: ret
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%1 = uitofp i32 %a to half
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ret half %1
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}
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define half @uitofp_zext_i32_to_f16(i32 zeroext %a) nounwind {
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; RV64IZFH-LABEL: uitofp_zext_i32_to_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
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; RV64IZFH-NEXT: ret
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%1 = uitofp i32 %a to half
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ret half %1
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}
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define half @sitofp_aext_i32_to_f16(i32 %a) nounwind {
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; RV64IZFH-LABEL: sitofp_aext_i32_to_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fcvt.h.w fa0, a0
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; RV64IZFH-NEXT: ret
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%1 = sitofp i32 %a to half
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ret half %1
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}
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define half @sitofp_sext_i32_to_f16(i32 signext %a) nounwind {
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; RV64IZFH-LABEL: sitofp_sext_i32_to_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fcvt.h.w fa0, a0
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; RV64IZFH-NEXT: ret
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%1 = sitofp i32 %a to half
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ret half %1
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}
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define half @sitofp_zext_i32_to_f16(i32 zeroext %a) nounwind {
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; RV64IZFH-LABEL: sitofp_zext_i32_to_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fcvt.h.w fa0, a0
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; RV64IZFH-NEXT: ret
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%1 = sitofp i32 %a to half
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ret half %1
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}
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