llvm-for-llvmta/test/CodeGen/X86/bit-test-shift.ll

19 lines
548 B
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
; <rdar://problem/8285015>
define i32 @x(i32 %t) nounwind readnone ssp {
; CHECK-LABEL: x:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: shll $23, %eax
; CHECK-NEXT: sarl $31, %eax
; CHECK-NEXT: andl $-26, %eax
; CHECK-NEXT: retl
entry:
%and = and i32 %t, 256
%tobool = icmp eq i32 %and, 0
%retval.0 = select i1 %tobool, i32 0, i32 -26
ret i32 %retval.0
}