293 lines
11 KiB
LLVM
293 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+bmi,+bmi2 < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-unknown"
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; Stack reload folding tests.
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;
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; By including a nop call with sideeffects we can force a partial register spill of the
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; relevant registers and check that the reload is correctly folded into the instruction.
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define i32 @stack_fold_bzhi_u32(i32 %a0, i32 %a1) {
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; CHECK-LABEL: stack_fold_bzhi_u32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: pushq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: pushq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: pushq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: pushq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 56
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; CHECK-NEXT: .cfi_offset %rbx, -56
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; CHECK-NEXT: .cfi_offset %r12, -48
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; CHECK-NEXT: .cfi_offset %r13, -40
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; CHECK-NEXT: .cfi_offset %r14, -32
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; CHECK-NEXT: .cfi_offset %r15, -24
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; CHECK-NEXT: .cfi_offset %rbp, -16
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; CHECK-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
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; CHECK-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
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; CHECK-NEXT: #APP
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; CHECK-NEXT: nop
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
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; CHECK-NEXT: bzhil %eax, {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Folded Reload
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: popq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: popq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: popq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: popq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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%1 = tail call i32 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
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%2 = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %a0, i32 %a1)
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ret i32 %2
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}
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declare i32 @llvm.x86.bmi.bzhi.32(i32, i32)
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define i64 @stack_fold_bzhi_u64(i64 %a0, i64 %a1) {
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; CHECK-LABEL: stack_fold_bzhi_u64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: pushq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: pushq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: pushq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: pushq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 56
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; CHECK-NEXT: .cfi_offset %rbx, -56
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; CHECK-NEXT: .cfi_offset %r12, -48
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; CHECK-NEXT: .cfi_offset %r13, -40
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; CHECK-NEXT: .cfi_offset %r14, -32
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; CHECK-NEXT: .cfi_offset %r15, -24
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; CHECK-NEXT: .cfi_offset %rbp, -16
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; CHECK-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: #APP
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; CHECK-NEXT: nop
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
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; CHECK-NEXT: bzhiq %rax, {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Folded Reload
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: popq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: popq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: popq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: popq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
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%2 = tail call i64 @llvm.x86.bmi.bzhi.64(i64 %a0, i64 %a1)
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ret i64 %2
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}
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declare i64 @llvm.x86.bmi.bzhi.64(i64, i64)
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define i32 @stack_fold_pdep_u32(i32 %a0, i32 %a1) {
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; CHECK-LABEL: stack_fold_pdep_u32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: pushq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: pushq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: pushq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: pushq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 56
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; CHECK-NEXT: .cfi_offset %rbx, -56
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; CHECK-NEXT: .cfi_offset %r12, -48
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; CHECK-NEXT: .cfi_offset %r13, -40
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; CHECK-NEXT: .cfi_offset %r14, -32
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; CHECK-NEXT: .cfi_offset %r15, -24
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; CHECK-NEXT: .cfi_offset %rbp, -16
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; CHECK-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
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; CHECK-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
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; CHECK-NEXT: #APP
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; CHECK-NEXT: nop
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
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; CHECK-NEXT: pdepl {{[-0-9]+}}(%r{{[sb]}}p), %eax, %eax # 4-byte Folded Reload
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: popq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: popq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: popq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: popq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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%1 = tail call i32 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
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%2 = tail call i32 @llvm.x86.bmi.pdep.32(i32 %a0, i32 %a1)
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ret i32 %2
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}
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declare i32 @llvm.x86.bmi.pdep.32(i32, i32)
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define i64 @stack_fold_pdep_u64(i64 %a0, i64 %a1) {
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; CHECK-LABEL: stack_fold_pdep_u64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: pushq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: pushq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: pushq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: pushq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 56
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; CHECK-NEXT: .cfi_offset %rbx, -56
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; CHECK-NEXT: .cfi_offset %r12, -48
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; CHECK-NEXT: .cfi_offset %r13, -40
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; CHECK-NEXT: .cfi_offset %r14, -32
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; CHECK-NEXT: .cfi_offset %r15, -24
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; CHECK-NEXT: .cfi_offset %rbp, -16
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; CHECK-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: #APP
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; CHECK-NEXT: nop
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
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; CHECK-NEXT: pdepq {{[-0-9]+}}(%r{{[sb]}}p), %rax, %rax # 8-byte Folded Reload
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: popq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: popq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: popq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: popq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
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%2 = tail call i64 @llvm.x86.bmi.pdep.64(i64 %a0, i64 %a1)
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ret i64 %2
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}
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declare i64 @llvm.x86.bmi.pdep.64(i64, i64)
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define i32 @stack_fold_pext_u32(i32 %a0, i32 %a1) {
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; CHECK-LABEL: stack_fold_pext_u32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: pushq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: pushq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: pushq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: pushq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 56
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; CHECK-NEXT: .cfi_offset %rbx, -56
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; CHECK-NEXT: .cfi_offset %r12, -48
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; CHECK-NEXT: .cfi_offset %r13, -40
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; CHECK-NEXT: .cfi_offset %r14, -32
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; CHECK-NEXT: .cfi_offset %r15, -24
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; CHECK-NEXT: .cfi_offset %rbp, -16
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; CHECK-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
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; CHECK-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
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; CHECK-NEXT: #APP
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; CHECK-NEXT: nop
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
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; CHECK-NEXT: pextl {{[-0-9]+}}(%r{{[sb]}}p), %eax, %eax # 4-byte Folded Reload
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: popq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: popq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: popq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: popq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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%1 = tail call i32 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
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%2 = tail call i32 @llvm.x86.bmi.pext.32(i32 %a0, i32 %a1)
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ret i32 %2
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}
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declare i32 @llvm.x86.bmi.pext.32(i32, i32)
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define i64 @stack_fold_pext_u64(i64 %a0, i64 %a1) {
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; CHECK-LABEL: stack_fold_pext_u64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: pushq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: pushq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: pushq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: pushq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 56
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; CHECK-NEXT: .cfi_offset %rbx, -56
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; CHECK-NEXT: .cfi_offset %r12, -48
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; CHECK-NEXT: .cfi_offset %r13, -40
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; CHECK-NEXT: .cfi_offset %r14, -32
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; CHECK-NEXT: .cfi_offset %r15, -24
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; CHECK-NEXT: .cfi_offset %rbp, -16
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; CHECK-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: #APP
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; CHECK-NEXT: nop
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
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; CHECK-NEXT: pextq {{[-0-9]+}}(%r{{[sb]}}p), %rax, %rax # 8-byte Folded Reload
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: popq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: popq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: popq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: popq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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%1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
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%2 = tail call i64 @llvm.x86.bmi.pext.64(i64 %a0, i64 %a1)
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ret i64 %2
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}
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declare i64 @llvm.x86.bmi.pext.64(i64, i64)
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