492 lines
13 KiB
LLVM
492 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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; Materializing constants
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; TODO: It would be preferable if anyext constant returns were sign rather
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; than zero extended. See PR39092. For now, mark returns as explicitly signext
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; (this matches what Clang would generate for equivalent C/C++ anyway).
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define signext i32 @zero() nounwind {
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; RV32I-LABEL: zero:
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; RV32I: # %bb.0:
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: zero:
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; RV64I: # %bb.0:
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; RV64I-NEXT: mv a0, zero
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; RV64I-NEXT: ret
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ret i32 0
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}
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define signext i32 @pos_small() nounwind {
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; RV32I-LABEL: pos_small:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, zero, 2047
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: pos_small:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, zero, 2047
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; RV64I-NEXT: ret
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ret i32 2047
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}
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define signext i32 @neg_small() nounwind {
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; RV32I-LABEL: neg_small:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, zero, -2048
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: neg_small:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, zero, -2048
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; RV64I-NEXT: ret
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ret i32 -2048
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}
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define signext i32 @pos_i32() nounwind {
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; RV32I-LABEL: pos_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 423811
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; RV32I-NEXT: addi a0, a0, -1297
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: pos_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 423811
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; RV64I-NEXT: addiw a0, a0, -1297
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; RV64I-NEXT: ret
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ret i32 1735928559
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}
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define signext i32 @neg_i32() nounwind {
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; RV32I-LABEL: neg_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 912092
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; RV32I-NEXT: addi a0, a0, -273
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: neg_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 912092
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; RV64I-NEXT: addiw a0, a0, -273
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; RV64I-NEXT: ret
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ret i32 -559038737
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}
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define signext i32 @pos_i32_hi20_only() nounwind {
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; RV32I-LABEL: pos_i32_hi20_only:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: pos_i32_hi20_only:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 16
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; RV64I-NEXT: ret
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ret i32 65536 ; 0x10000
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}
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define signext i32 @neg_i32_hi20_only() nounwind {
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; RV32I-LABEL: neg_i32_hi20_only:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 1048560
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: neg_i32_hi20_only:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 1048560
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; RV64I-NEXT: ret
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ret i32 -65536 ; -0x10000
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}
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; This can be materialized with ADDI+SLLI, improving compressibility.
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define signext i32 @imm_left_shifted_addi() nounwind {
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; RV32I-LABEL: imm_left_shifted_addi:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 32
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; RV32I-NEXT: addi a0, a0, -64
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm_left_shifted_addi:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 32
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; RV64I-NEXT: addiw a0, a0, -64
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; RV64I-NEXT: ret
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ret i32 131008 ; 0x1FFC0
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}
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; This can be materialized with ADDI+SRLI, improving compressibility.
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define signext i32 @imm_right_shifted_addi() nounwind {
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; RV32I-LABEL: imm_right_shifted_addi:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 524288
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; RV32I-NEXT: addi a0, a0, -1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm_right_shifted_addi:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 524288
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; RV64I-NEXT: addiw a0, a0, -1
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; RV64I-NEXT: ret
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ret i32 2147483647 ; 0x7FFFFFFF
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}
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; This can be materialized with LUI+SRLI, improving compressibility.
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define signext i32 @imm_right_shifted_lui() nounwind {
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; RV32I-LABEL: imm_right_shifted_lui:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 56
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; RV32I-NEXT: addi a0, a0, 580
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm_right_shifted_lui:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 56
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; RV64I-NEXT: addiw a0, a0, 580
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; RV64I-NEXT: ret
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ret i32 229956 ; 0x38244
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}
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define i64 @imm64_1() nounwind {
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; RV32I-LABEL: imm64_1:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 524288
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; RV32I-NEXT: mv a1, zero
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm64_1:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, zero, 1
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; RV64I-NEXT: slli a0, a0, 31
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; RV64I-NEXT: ret
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ret i64 2147483648 ; 0x8000_0000
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}
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; TODO: This and similar constants with all 0s in the upper bits and all 1s in
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; the lower bits could be lowered to addi a0, zero, -1 followed by a logical
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; right shift.
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define i64 @imm64_2() nounwind {
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; RV32I-LABEL: imm64_2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, zero, -1
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; RV32I-NEXT: mv a1, zero
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm64_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, zero, 1
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: addi a0, a0, -1
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; RV64I-NEXT: ret
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ret i64 4294967295 ; 0xFFFF_FFFF
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}
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define i64 @imm64_3() nounwind {
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; RV32I-LABEL: imm64_3:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a1, zero, 1
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm64_3:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, zero, 1
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: ret
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ret i64 4294967296 ; 0x1_0000_0000
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}
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define i64 @imm64_4() nounwind {
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; RV32I-LABEL: imm64_4:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 524288
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm64_4:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, zero, -1
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; RV64I-NEXT: slli a0, a0, 63
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; RV64I-NEXT: ret
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ret i64 9223372036854775808 ; 0x8000_0000_0000_0000
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}
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define i64 @imm64_5() nounwind {
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; RV32I-LABEL: imm64_5:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 524288
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm64_5:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, zero, -1
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; RV64I-NEXT: slli a0, a0, 63
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; RV64I-NEXT: ret
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ret i64 -9223372036854775808 ; 0x8000_0000_0000_0000
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}
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define i64 @imm64_6() nounwind {
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; RV32I-LABEL: imm64_6:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 74565
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; RV32I-NEXT: addi a1, a0, 1656
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm64_6:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 9321
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; RV64I-NEXT: addiw a0, a0, -1329
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; RV64I-NEXT: slli a0, a0, 35
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; RV64I-NEXT: ret
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ret i64 1311768464867721216 ; 0x1234_5678_0000_0000
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}
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define i64 @imm64_7() nounwind {
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; RV32I-LABEL: imm64_7:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 45056
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; RV32I-NEXT: addi a0, a0, 15
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; RV32I-NEXT: lui a1, 458752
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm64_7:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, zero, 7
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; RV64I-NEXT: slli a0, a0, 36
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; RV64I-NEXT: addi a0, a0, 11
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; RV64I-NEXT: slli a0, a0, 24
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; RV64I-NEXT: addi a0, a0, 15
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; RV64I-NEXT: ret
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ret i64 8070450532432478223 ; 0x7000_0000_0B00_000F
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}
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; TODO: it can be preferable to put constants that are expensive to materialise
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; into the constant pool, especially for -Os.
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define i64 @imm64_8() nounwind {
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; RV32I-LABEL: imm64_8:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 633806
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; RV32I-NEXT: addi a0, a0, -272
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; RV32I-NEXT: lui a1, 74565
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; RV32I-NEXT: addi a1, a1, 1656
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm64_8:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 583
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; RV64I-NEXT: addiw a0, a0, -1875
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; RV64I-NEXT: slli a0, a0, 14
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; RV64I-NEXT: addi a0, a0, -947
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; RV64I-NEXT: slli a0, a0, 12
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; RV64I-NEXT: addi a0, a0, 1511
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; RV64I-NEXT: slli a0, a0, 13
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; RV64I-NEXT: addi a0, a0, -272
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; RV64I-NEXT: ret
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ret i64 1311768467463790320 ; 0x1234_5678_9ABC_DEF0
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}
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define i64 @imm64_9() nounwind {
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; RV32I-LABEL: imm64_9:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, zero, -1
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; RV32I-NEXT: addi a1, zero, -1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm64_9:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, zero, -1
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; RV64I-NEXT: ret
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ret i64 -1
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}
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; Various cases where extraneous ADDIs can be inserted where a (left shifted)
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; LUI suffices.
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define i64 @imm_left_shifted_lui_1() nounwind {
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; RV32I-LABEL: imm_left_shifted_lui_1:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 524290
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; RV32I-NEXT: mv a1, zero
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm_left_shifted_lui_1:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 64
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; RV64I-NEXT: addiw a0, a0, 1
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; RV64I-NEXT: slli a0, a0, 13
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; RV64I-NEXT: ret
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ret i64 2147491840 ; 0x8000_2000
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}
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define i64 @imm_left_shifted_lui_2() nounwind {
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; RV32I-LABEL: imm_left_shifted_lui_2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 4
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; RV32I-NEXT: addi a1, zero, 1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm_left_shifted_lui_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 64
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; RV64I-NEXT: addiw a0, a0, 1
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; RV64I-NEXT: slli a0, a0, 14
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; RV64I-NEXT: ret
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ret i64 4294983680 ; 0x1_0000_4000
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}
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define i64 @imm_left_shifted_lui_3() nounwind {
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; RV32I-LABEL: imm_left_shifted_lui_3:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 1
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; RV32I-NEXT: addi a1, a0, 1
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm_left_shifted_lui_3:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 1
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; RV64I-NEXT: addiw a0, a0, 1
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: ret
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ret i64 17596481011712 ; 0x1001_0000_0000
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}
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; Various cases where extraneous ADDIs can be inserted where a (right shifted)
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; LUI suffices, or where multiple ADDIs can be used instead of a single LUI.
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define i64 @imm_right_shifted_lui_1() nounwind {
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; RV32I-LABEL: imm_right_shifted_lui_1:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 1048575
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; RV32I-NEXT: addi a0, a0, 1
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; RV32I-NEXT: lui a1, 16
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; RV32I-NEXT: addi a1, a1, -1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm_right_shifted_lui_1:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, zero, 1
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; RV64I-NEXT: slli a0, a0, 36
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; RV64I-NEXT: addi a0, a0, -1
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; RV64I-NEXT: slli a0, a0, 12
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; RV64I-NEXT: addi a0, a0, 1
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; RV64I-NEXT: ret
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ret i64 281474976706561 ; 0xFFFF_FFFF_F001
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}
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define i64 @imm_right_shifted_lui_2() nounwind {
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; RV32I-LABEL: imm_right_shifted_lui_2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 1048575
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; RV32I-NEXT: addi a0, a0, 1
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; RV32I-NEXT: addi a1, zero, 255
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm_right_shifted_lui_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 65536
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; RV64I-NEXT: addiw a0, a0, -1
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; RV64I-NEXT: slli a0, a0, 12
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; RV64I-NEXT: addi a0, a0, 1
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; RV64I-NEXT: ret
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ret i64 1099511623681 ; 0xFF_FFFF_F001
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}
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; We can materialize the upper bits with a single (shifted) LUI, but that option
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; can be missed due to the lower bits, which aren't just 1s or just 0s.
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define i64 @imm_decoupled_lui_addi() nounwind {
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; RV32I-LABEL: imm_decoupled_lui_addi:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, zero, -3
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; RV32I-NEXT: lui a1, 1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: imm_decoupled_lui_addi:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 1
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; RV64I-NEXT: addiw a0, a0, 1
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: addi a0, a0, -3
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; RV64I-NEXT: ret
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ret i64 17596481011709 ; 0x1000_FFFF_FFFD
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}
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; This constant can be materialized for RV64 with LUI+SRLI+XORI.
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define i64 @imm_end_xori_1() nounwind {
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; RV32I-LABEL: imm_end_xori_1:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 8192
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; RV32I-NEXT: addi a0, a0, -1
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; RV32I-NEXT: lui a1, 917504
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; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_end_xori_1:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi a0, zero, -1
|
|
; RV64I-NEXT: slli a0, a0, 36
|
|
; RV64I-NEXT: addi a0, a0, 1
|
|
; RV64I-NEXT: slli a0, a0, 25
|
|
; RV64I-NEXT: addi a0, a0, -1
|
|
; RV64I-NEXT: ret
|
|
ret i64 -2305843009180139521 ; 0xE000_0000_01FF_FFFF
|
|
}
|
|
|
|
; This constant can be materialized for RV64 with ADDI+SLLI+ADDI+ADDI.
|
|
|
|
define i64 @imm_end_2addi_1() nounwind {
|
|
; RV32I-LABEL: imm_end_2addi_1:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 1048575
|
|
; RV32I-NEXT: addi a0, a0, 2047
|
|
; RV32I-NEXT: lui a1, 1048512
|
|
; RV32I-NEXT: addi a1, a1, 127
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_end_2addi_1:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi a0, zero, -2047
|
|
; RV64I-NEXT: slli a0, a0, 27
|
|
; RV64I-NEXT: addi a0, a0, -1
|
|
; RV64I-NEXT: slli a0, a0, 12
|
|
; RV64I-NEXT: addi a0, a0, 2047
|
|
; RV64I-NEXT: ret
|
|
ret i64 -1125350151030785 ; 0xFFFC_007F_FFFF_F7FF
|
|
}
|
|
|
|
; This constant can be more efficiently materialized for RV64 if we use two
|
|
; registers instead of one.
|
|
|
|
define i64 @imm_2reg_1() nounwind {
|
|
; RV32I-LABEL: imm_2reg_1:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: lui a0, 74565
|
|
; RV32I-NEXT: addi a0, a0, 1656
|
|
; RV32I-NEXT: lui a1, 983040
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: imm_2reg_1:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi a0, zero, -1
|
|
; RV64I-NEXT: slli a0, a0, 35
|
|
; RV64I-NEXT: addi a0, a0, 9
|
|
; RV64I-NEXT: slli a0, a0, 13
|
|
; RV64I-NEXT: addi a0, a0, 837
|
|
; RV64I-NEXT: slli a0, a0, 12
|
|
; RV64I-NEXT: addi a0, a0, 1656
|
|
; RV64I-NEXT: ret
|
|
ret i64 -1152921504301427080 ; 0xF000_0000_1234_5678
|
|
}
|