109 lines
4.3 KiB
LLVM
109 lines
4.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -mattr=+avx512ifma | FileCheck %s --check-prefixes=CHECK,X86
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; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx512ifma | FileCheck %s --check-prefixes=CHECK,X64
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; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/avx512ifma-builtins.c
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define <8 x i64> @test_mm512_madd52hi_epu64(<8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z) {
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; CHECK-LABEL: test_mm512_madd52hi_epu64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vpmadd52huq %zmm2, %zmm1, %zmm0
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; CHECK-NEXT: ret{{[l|q]}}
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entry:
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%0 = tail call <8 x i64> @llvm.x86.avx512.vpmadd52h.uq.512(<8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z)
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ret <8 x i64> %0
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}
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define <8 x i64> @test_mm512_mask_madd52hi_epu64(<8 x i64> %__W, i8 zeroext %__M, <8 x i64> %__X, <8 x i64> %__Y) {
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; X86-LABEL: test_mm512_mask_madd52hi_epu64:
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; X86: # %bb.0: # %entry
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; X86-NEXT: movb {{[0-9]+}}(%esp), %al
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; X86-NEXT: kmovw %eax, %k1
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; X86-NEXT: vpmadd52huq %zmm2, %zmm1, %zmm0 {%k1}
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; X86-NEXT: retl
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;
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; X64-LABEL: test_mm512_mask_madd52hi_epu64:
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; X64: # %bb.0: # %entry
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; X64-NEXT: kmovw %edi, %k1
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; X64-NEXT: vpmadd52huq %zmm2, %zmm1, %zmm0 {%k1}
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; X64-NEXT: retq
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entry:
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%0 = tail call <8 x i64> @llvm.x86.avx512.vpmadd52h.uq.512(<8 x i64> %__W, <8 x i64> %__X, <8 x i64> %__Y)
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%1 = bitcast i8 %__M to <8 x i1>
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%2 = select <8 x i1> %1, <8 x i64> %0, <8 x i64> %__W
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ret <8 x i64> %2
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}
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define <8 x i64> @test_mm512_maskz_madd52hi_epu64(i8 zeroext %__M, <8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z) {
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; X86-LABEL: test_mm512_maskz_madd52hi_epu64:
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; X86: # %bb.0: # %entry
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; X86-NEXT: movb {{[0-9]+}}(%esp), %al
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; X86-NEXT: kmovw %eax, %k1
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; X86-NEXT: vpmadd52huq %zmm2, %zmm1, %zmm0 {%k1} {z}
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; X86-NEXT: retl
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;
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; X64-LABEL: test_mm512_maskz_madd52hi_epu64:
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; X64: # %bb.0: # %entry
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; X64-NEXT: kmovw %edi, %k1
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; X64-NEXT: vpmadd52huq %zmm2, %zmm1, %zmm0 {%k1} {z}
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; X64-NEXT: retq
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entry:
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%0 = tail call <8 x i64> @llvm.x86.avx512.vpmadd52h.uq.512(<8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z)
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%1 = bitcast i8 %__M to <8 x i1>
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%2 = select <8 x i1> %1, <8 x i64> %0, <8 x i64> zeroinitializer
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ret <8 x i64> %2
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}
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define <8 x i64> @test_mm512_madd52lo_epu64(<8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z) {
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; CHECK-LABEL: test_mm512_madd52lo_epu64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vpmadd52luq %zmm2, %zmm1, %zmm0
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; CHECK-NEXT: ret{{[l|q]}}
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entry:
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%0 = tail call <8 x i64> @llvm.x86.avx512.vpmadd52l.uq.512(<8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z)
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ret <8 x i64> %0
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}
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define <8 x i64> @test_mm512_mask_madd52lo_epu64(<8 x i64> %__W, i8 zeroext %__M, <8 x i64> %__X, <8 x i64> %__Y) {
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; X86-LABEL: test_mm512_mask_madd52lo_epu64:
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; X86: # %bb.0: # %entry
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; X86-NEXT: movb {{[0-9]+}}(%esp), %al
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; X86-NEXT: kmovw %eax, %k1
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; X86-NEXT: vpmadd52luq %zmm2, %zmm1, %zmm0 {%k1}
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; X86-NEXT: retl
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;
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; X64-LABEL: test_mm512_mask_madd52lo_epu64:
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; X64: # %bb.0: # %entry
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; X64-NEXT: kmovw %edi, %k1
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; X64-NEXT: vpmadd52luq %zmm2, %zmm1, %zmm0 {%k1}
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; X64-NEXT: retq
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entry:
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%0 = tail call <8 x i64> @llvm.x86.avx512.vpmadd52l.uq.512(<8 x i64> %__W, <8 x i64> %__X, <8 x i64> %__Y)
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%1 = bitcast i8 %__M to <8 x i1>
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%2 = select <8 x i1> %1, <8 x i64> %0, <8 x i64> %__W
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ret <8 x i64> %2
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}
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define <8 x i64> @test_mm512_maskz_madd52lo_epu64(i8 zeroext %__M, <8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z) {
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; X86-LABEL: test_mm512_maskz_madd52lo_epu64:
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; X86: # %bb.0: # %entry
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; X86-NEXT: movb {{[0-9]+}}(%esp), %al
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; X86-NEXT: kmovw %eax, %k1
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; X86-NEXT: vpmadd52luq %zmm2, %zmm1, %zmm0 {%k1} {z}
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; X86-NEXT: retl
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;
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; X64-LABEL: test_mm512_maskz_madd52lo_epu64:
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; X64: # %bb.0: # %entry
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; X64-NEXT: kmovw %edi, %k1
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; X64-NEXT: vpmadd52luq %zmm2, %zmm1, %zmm0 {%k1} {z}
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; X64-NEXT: retq
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entry:
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%0 = tail call <8 x i64> @llvm.x86.avx512.vpmadd52l.uq.512(<8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z)
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%1 = bitcast i8 %__M to <8 x i1>
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%2 = select <8 x i1> %1, <8 x i64> %0, <8 x i64> zeroinitializer
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ret <8 x i64> %2
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}
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declare <8 x i64> @llvm.x86.avx512.vpmadd52h.uq.512(<8 x i64>, <8 x i64>, <8 x i64>)
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declare <8 x i64> @llvm.x86.avx512.vpmadd52l.uq.512(<8 x i64>, <8 x i64>, <8 x i64>)
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