377 lines
14 KiB
LLVM
377 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -indvars -S | FileCheck %s
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; Provide legal integer types.
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target datalayout = "n8:16:32:64"
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; CHECK-NOT: sext
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define i64 @test(i64* nocapture %first, i32 %count) nounwind readonly {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[T0:%.*]] = icmp sgt i32 [[COUNT:%.*]], 0
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; CHECK-NEXT: br i1 [[T0]], label [[BB_NPH:%.*]], label [[BB2:%.*]]
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; CHECK: bb.nph:
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; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[COUNT]] to i64
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; CHECK-NEXT: br label [[BB:%.*]]
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; CHECK: bb:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[BB1:%.*]] ], [ 0, [[BB_NPH]] ]
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; CHECK-NEXT: [[RESULT_02:%.*]] = phi i64 [ [[T5:%.*]], [[BB1]] ], [ 0, [[BB_NPH]] ]
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; CHECK-NEXT: [[T2:%.*]] = getelementptr i64, i64* [[FIRST:%.*]], i64 [[INDVARS_IV]]
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; CHECK-NEXT: [[T3:%.*]] = load i64, i64* [[T2]], align 8
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; CHECK-NEXT: [[T4:%.*]] = lshr i64 [[T3]], 4
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; CHECK-NEXT: [[T5]] = add i64 [[T4]], [[RESULT_02]]
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: br label [[BB1]]
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; CHECK: bb1:
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]]
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[BB]], label [[BB1_BB2_CRIT_EDGE:%.*]]
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; CHECK: bb1.bb2_crit_edge:
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; CHECK-NEXT: [[DOTLCSSA:%.*]] = phi i64 [ [[T5]], [[BB1]] ]
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; CHECK-NEXT: br label [[BB2]]
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; CHECK: bb2:
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; CHECK-NEXT: [[RESULT_0_LCSSA:%.*]] = phi i64 [ [[DOTLCSSA]], [[BB1_BB2_CRIT_EDGE]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: ret i64 [[RESULT_0_LCSSA]]
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;
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entry:
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%t0 = icmp sgt i32 %count, 0 ; <i1> [#uses=1]
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br i1 %t0, label %bb.nph, label %bb2
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bb.nph: ; preds = %entry
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br label %bb
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bb: ; preds = %bb1, %bb.nph
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%result.02 = phi i64 [ %t5, %bb1 ], [ 0, %bb.nph ] ; <i64> [#uses=1]
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%n.01 = phi i32 [ %t6, %bb1 ], [ 0, %bb.nph ] ; <i32> [#uses=2]
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%t1 = sext i32 %n.01 to i64 ; <i64> [#uses=1]
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%t2 = getelementptr i64, i64* %first, i64 %t1 ; <i64*> [#uses=1]
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%t3 = load i64, i64* %t2, align 8 ; <i64> [#uses=1]
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%t4 = lshr i64 %t3, 4 ; <i64> [#uses=1]
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%t5 = add i64 %t4, %result.02 ; <i64> [#uses=2]
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%t6 = add i32 %n.01, 1 ; <i32> [#uses=2]
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br label %bb1
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bb1: ; preds = %bb
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%t7 = icmp slt i32 %t6, %count ; <i1> [#uses=1]
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br i1 %t7, label %bb, label %bb1.bb2_crit_edge
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bb1.bb2_crit_edge: ; preds = %bb1
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%.lcssa = phi i64 [ %t5, %bb1 ] ; <i64> [#uses=1]
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br label %bb2
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bb2: ; preds = %bb1.bb2_crit_edge, %entry
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%result.0.lcssa = phi i64 [ %.lcssa, %bb1.bb2_crit_edge ], [ 0, %entry ] ; <i64> [#uses=1]
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ret i64 %result.0.lcssa
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}
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define void @foo(i16 signext %N, i32* nocapture %P) nounwind {
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; CHECK-LABEL: @foo(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[T0:%.*]] = icmp sgt i16 [[N:%.*]], 0
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; CHECK-NEXT: br i1 [[T0]], label [[BB_NPH:%.*]], label [[RETURN:%.*]]
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; CHECK: bb.nph:
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; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i16 [[N]] to i64
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; CHECK-NEXT: br label [[BB:%.*]]
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; CHECK: bb:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[BB1:%.*]] ], [ 0, [[BB_NPH]] ]
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; CHECK-NEXT: [[T2:%.*]] = getelementptr i32, i32* [[P:%.*]], i64 [[INDVARS_IV]]
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; CHECK-NEXT: store i32 123, i32* [[T2]], align 4
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: br label [[BB1]]
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; CHECK: bb1:
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]]
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[BB]], label [[BB1_RETURN_CRIT_EDGE:%.*]]
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; CHECK: bb1.return_crit_edge:
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; CHECK-NEXT: br label [[RETURN]]
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; CHECK: return:
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; CHECK-NEXT: ret void
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;
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entry:
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%t0 = icmp sgt i16 %N, 0 ; <i1> [#uses=1]
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br i1 %t0, label %bb.nph, label %return
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bb.nph: ; preds = %entry
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br label %bb
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bb: ; preds = %bb1, %bb.nph
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%i.01 = phi i16 [ %t3, %bb1 ], [ 0, %bb.nph ] ; <i16> [#uses=2]
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%t1 = sext i16 %i.01 to i64 ; <i64> [#uses=1]
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%t2 = getelementptr i32, i32* %P, i64 %t1 ; <i32*> [#uses=1]
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store i32 123, i32* %t2, align 4
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%t3 = add i16 %i.01, 1 ; <i16> [#uses=2]
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br label %bb1
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bb1: ; preds = %bb
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%t4 = icmp slt i16 %t3, %N ; <i1> [#uses=1]
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br i1 %t4, label %bb, label %bb1.return_crit_edge
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bb1.return_crit_edge: ; preds = %bb1
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br label %return
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return: ; preds = %bb1.return_crit_edge, %entry
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ret void
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}
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; Test cases from PR1301:
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define void @kinds__srangezero([21 x i32]* nocapture %a) nounwind {
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; CHECK-LABEL: @kinds__srangezero(
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; CHECK-NEXT: bb.thread:
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; CHECK-NEXT: br label [[BB:%.*]]
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; CHECK: bb:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i32 [ [[INDVARS_IV_NEXT:%.*]], [[BB]] ], [ -10, [[BB_THREAD:%.*]] ]
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; CHECK-NEXT: [[TMP4:%.*]] = add nsw i32 [[INDVARS_IV]], 10
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; CHECK-NEXT: [[TMP5:%.*]] = getelementptr [21 x i32], [21 x i32]* [[A:%.*]], i32 0, i32 [[TMP4]]
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; CHECK-NEXT: store i32 0, i32* [[TMP5]], align 4
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i32 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INDVARS_IV_NEXT]], 11
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[RETURN:%.*]], label [[BB]]
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; CHECK: return:
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; CHECK-NEXT: ret void
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;
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bb.thread:
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br label %bb
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bb: ; preds = %bb, %bb.thread
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%i.0.reg2mem.0 = phi i8 [ -10, %bb.thread ], [ %tmp7, %bb ] ; <i8> [#uses=2]
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%tmp12 = sext i8 %i.0.reg2mem.0 to i32 ; <i32> [#uses=1]
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%tmp4 = add i32 %tmp12, 10 ; <i32> [#uses=1]
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%tmp5 = getelementptr [21 x i32], [21 x i32]* %a, i32 0, i32 %tmp4 ; <i32*> [#uses=1]
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store i32 0, i32* %tmp5
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%tmp7 = add i8 %i.0.reg2mem.0, 1 ; <i8> [#uses=2]
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%0 = icmp sgt i8 %tmp7, 10 ; <i1> [#uses=1]
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br i1 %0, label %return, label %bb
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return: ; preds = %bb
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ret void
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}
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define void @kinds__urangezero([21 x i32]* nocapture %a) nounwind {
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; CHECK-LABEL: @kinds__urangezero(
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; CHECK-NEXT: bb.thread:
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; CHECK-NEXT: br label [[BB:%.*]]
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; CHECK: bb:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i32 [ [[INDVARS_IV_NEXT:%.*]], [[BB]] ], [ 10, [[BB_THREAD:%.*]] ]
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; CHECK-NEXT: [[TMP4:%.*]] = add nsw i32 [[INDVARS_IV]], -10
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; CHECK-NEXT: [[TMP5:%.*]] = getelementptr [21 x i32], [21 x i32]* [[A:%.*]], i32 0, i32 [[TMP4]]
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; CHECK-NEXT: store i32 0, i32* [[TMP5]], align 4
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i32 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INDVARS_IV_NEXT]], 31
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[RETURN:%.*]], label [[BB]]
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; CHECK: return:
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; CHECK-NEXT: ret void
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;
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bb.thread:
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br label %bb
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bb: ; preds = %bb, %bb.thread
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%i.0.reg2mem.0 = phi i8 [ 10, %bb.thread ], [ %tmp7, %bb ] ; <i8> [#uses=2]
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%tmp12 = sext i8 %i.0.reg2mem.0 to i32 ; <i32> [#uses=1]
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%tmp4 = add i32 %tmp12, -10 ; <i32> [#uses=1]
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%tmp5 = getelementptr [21 x i32], [21 x i32]* %a, i32 0, i32 %tmp4 ; <i32*> [#uses=1]
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store i32 0, i32* %tmp5
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%tmp7 = add i8 %i.0.reg2mem.0, 1 ; <i8> [#uses=2]
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%0 = icmp sgt i8 %tmp7, 30 ; <i1> [#uses=1]
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br i1 %0, label %return, label %bb
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return: ; preds = %bb
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ret void
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}
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define void @promote_latch_condition_decrementing_loop_01(i32* %p, i32* %a) {
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; CHECK-LABEL: @promote_latch_condition_decrementing_loop_01(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[LEN:%.*]] = load i32, i32* [[P:%.*]], align 4, [[RNG0:!range !.*]]
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; CHECK-NEXT: [[LEN_MINUS_1:%.*]] = add nsw i32 [[LEN]], -1
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; CHECK-NEXT: [[ZERO_CHECK:%.*]] = icmp eq i32 [[LEN]], 0
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; CHECK-NEXT: br i1 [[ZERO_CHECK]], label [[LOOPEXIT:%.*]], label [[PREHEADER:%.*]]
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; CHECK: preheader:
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; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[LEN_MINUS_1]] to i64
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loopexit.loopexit:
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; CHECK-NEXT: br label [[LOOPEXIT]]
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; CHECK: loopexit:
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; CHECK-NEXT: ret void
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; CHECK: loop:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ], [ [[TMP0]], [[PREHEADER]] ]
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; CHECK-NEXT: [[EL:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDVARS_IV]]
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; CHECK-NEXT: store atomic i32 0, i32* [[EL]] unordered, align 4
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; CHECK-NEXT: [[LOOPCOND:%.*]] = icmp slt i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], -1
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; CHECK-NEXT: br i1 [[LOOPCOND]], label [[LOOPEXIT_LOOPEXIT:%.*]], label [[LOOP]]
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;
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entry:
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%len = load i32, i32* %p, align 4, !range !0
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%len.minus.1 = add nsw i32 %len, -1
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%zero_check = icmp eq i32 %len, 0
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br i1 %zero_check, label %loopexit, label %preheader
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preheader:
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br label %loop
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loopexit:
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ret void
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loop:
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%iv = phi i32 [ %iv.next, %loop ], [ %len.minus.1, %preheader ]
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%iv.wide = zext i32 %iv to i64
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%el = getelementptr inbounds i32, i32* %a, i64 %iv.wide
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store atomic i32 0, i32* %el unordered, align 4
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%iv.next = add nsw i32 %iv, -1
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%loopcond = icmp slt i32 %iv, 1
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br i1 %loopcond, label %loopexit, label %loop
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}
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define void @promote_latch_condition_decrementing_loop_02(i32* %p, i32* %a) {
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; CHECK-LABEL: @promote_latch_condition_decrementing_loop_02(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[LEN:%.*]] = load i32, i32* [[P:%.*]], align 4, [[RNG0]]
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; CHECK-NEXT: [[ZERO_CHECK:%.*]] = icmp eq i32 [[LEN]], 0
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; CHECK-NEXT: br i1 [[ZERO_CHECK]], label [[LOOPEXIT:%.*]], label [[PREHEADER:%.*]]
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; CHECK: preheader:
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; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[LEN]] to i64
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loopexit.loopexit:
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; CHECK-NEXT: br label [[LOOPEXIT]]
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; CHECK: loopexit:
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; CHECK-NEXT: ret void
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; CHECK: loop:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ], [ [[TMP0]], [[PREHEADER]] ]
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; CHECK-NEXT: [[EL:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDVARS_IV]]
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; CHECK-NEXT: store atomic i32 0, i32* [[EL]] unordered, align 4
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], -1
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; CHECK-NEXT: [[LOOPCOND:%.*]] = icmp slt i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: br i1 [[LOOPCOND]], label [[LOOPEXIT_LOOPEXIT:%.*]], label [[LOOP]]
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;
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entry:
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%len = load i32, i32* %p, align 4, !range !0
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%zero_check = icmp eq i32 %len, 0
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br i1 %zero_check, label %loopexit, label %preheader
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preheader:
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br label %loop
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loopexit:
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ret void
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loop:
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%iv = phi i32 [ %iv.next, %loop ], [ %len, %preheader ]
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%iv.wide = zext i32 %iv to i64
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%el = getelementptr inbounds i32, i32* %a, i64 %iv.wide
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store atomic i32 0, i32* %el unordered, align 4
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%iv.next = add nsw i32 %iv, -1
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%loopcond = icmp slt i32 %iv, 1
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br i1 %loopcond, label %loopexit, label %loop
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}
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define void @promote_latch_condition_decrementing_loop_03(i32* %p, i32* %a) {
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; CHECK-LABEL: @promote_latch_condition_decrementing_loop_03(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[LEN:%.*]] = load i32, i32* [[P:%.*]], align 4, [[RNG0]]
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; CHECK-NEXT: [[ZERO_CHECK:%.*]] = icmp eq i32 [[LEN]], 0
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; CHECK-NEXT: br i1 [[ZERO_CHECK]], label [[LOOPEXIT:%.*]], label [[PREHEADER:%.*]]
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; CHECK: preheader:
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; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[LEN]] to i64
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; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[TMP0]], 1
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loopexit.loopexit:
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; CHECK-NEXT: br label [[LOOPEXIT]]
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; CHECK: loopexit:
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; CHECK-NEXT: ret void
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; CHECK: loop:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ], [ [[TMP1]], [[PREHEADER]] ]
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; CHECK-NEXT: [[EL:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDVARS_IV]]
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; CHECK-NEXT: store atomic i32 0, i32* [[EL]] unordered, align 4
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], -1
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; CHECK-NEXT: [[LOOPCOND:%.*]] = icmp slt i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: br i1 [[LOOPCOND]], label [[LOOPEXIT_LOOPEXIT:%.*]], label [[LOOP]]
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;
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entry:
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%len = load i32, i32* %p, align 4, !range !0
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%len.plus.1 = add i32 %len, 1
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%zero_check = icmp eq i32 %len, 0
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br i1 %zero_check, label %loopexit, label %preheader
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preheader:
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br label %loop
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loopexit:
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ret void
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loop:
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%iv = phi i32 [ %iv.next, %loop ], [ %len.plus.1, %preheader ]
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%iv.wide = zext i32 %iv to i64
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%el = getelementptr inbounds i32, i32* %a, i64 %iv.wide
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store atomic i32 0, i32* %el unordered, align 4
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%iv.next = add nsw i32 %iv, -1
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%loopcond = icmp slt i32 %iv, 1
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br i1 %loopcond, label %loopexit, label %loop
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}
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define void @promote_latch_condition_decrementing_loop_04(i32* %p, i32* %a, i1 %cond) {
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; CHECK-LABEL: @promote_latch_condition_decrementing_loop_04(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[LEN:%.*]] = load i32, i32* [[P:%.*]], align 4, [[RNG0]]
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; CHECK-NEXT: [[LEN_MINUS_1:%.*]] = add nsw i32 [[LEN]], -1
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; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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; CHECK: if.true:
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; CHECK-NEXT: br label [[MERGE:%.*]]
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; CHECK: if.false:
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; CHECK-NEXT: br label [[MERGE]]
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; CHECK: merge:
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; CHECK-NEXT: [[IV_START:%.*]] = phi i32 [ [[LEN]], [[IF_TRUE]] ], [ [[LEN_MINUS_1]], [[IF_FALSE]] ]
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; CHECK-NEXT: [[ZERO_CHECK:%.*]] = icmp eq i32 [[LEN]], 0
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; CHECK-NEXT: br i1 [[ZERO_CHECK]], label [[LOOPEXIT:%.*]], label [[PREHEADER:%.*]]
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; CHECK: preheader:
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; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[IV_START]] to i64
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loopexit.loopexit:
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; CHECK-NEXT: br label [[LOOPEXIT]]
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; CHECK: loopexit:
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; CHECK-NEXT: ret void
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; CHECK: loop:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ], [ [[TMP0]], [[PREHEADER]] ]
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; CHECK-NEXT: [[EL:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDVARS_IV]]
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; CHECK-NEXT: store atomic i32 0, i32* [[EL]] unordered, align 4
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; CHECK-NEXT: [[LOOPCOND:%.*]] = icmp slt i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], -1
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; CHECK-NEXT: br i1 [[LOOPCOND]], label [[LOOPEXIT_LOOPEXIT:%.*]], label [[LOOP]]
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;
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entry:
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%len = load i32, i32* %p, align 4, !range !0
|
|
%len.minus.1 = add nsw i32 %len, -1
|
|
br i1 %cond, label %if.true, label %if.false
|
|
|
|
if.true:
|
|
br label %merge
|
|
|
|
if.false:
|
|
br label %merge
|
|
|
|
merge:
|
|
%iv_start = phi i32 [ %len, %if.true ], [%len.minus.1, %if.false ]
|
|
%zero_check = icmp eq i32 %len, 0
|
|
br i1 %zero_check, label %loopexit, label %preheader
|
|
|
|
preheader:
|
|
br label %loop
|
|
|
|
loopexit:
|
|
ret void
|
|
|
|
loop:
|
|
%iv = phi i32 [ %iv.next, %loop ], [ %iv_start, %preheader ]
|
|
%iv.wide = zext i32 %iv to i64
|
|
%el = getelementptr inbounds i32, i32* %a, i64 %iv.wide
|
|
store atomic i32 0, i32* %el unordered, align 4
|
|
%iv.next = add nsw i32 %iv, -1
|
|
%loopcond = icmp slt i32 %iv, 1
|
|
br i1 %loopcond, label %loopexit, label %loop
|
|
}
|
|
|
|
!0 = !{i32 0, i32 2147483647}
|