forked from BSB-WS23/mpstubs
49 lines
1.9 KiB
C++
49 lines
1.9 KiB
C++
/*! \file
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* \brief Structures and macros for accessing \ref LAPIC "the local APIC".
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*/
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#pragma once
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#include "types.h"
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namespace LAPIC {
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// Memory Mapped Base Address
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extern volatile uintptr_t base_address;
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typedef uint32_t Register;
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/*! \brief Register Offset Index
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*
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* \see [ISDMv3 10.4.1 The Local APIC Block Diagram](intel_manual_vol3.pdf#page=368)
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*/
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enum Index : uint16_t {
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IDENTIFICATION = 0x020, ///< Local APIC ID Register, RO (sometimes R/W). Do not change!
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VERSION = 0x030, ///< Local APIC Version Register, RO
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TASK_PRIORITY = 0x080, ///< Task Priority Register, R/W
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EOI = 0x0b0, ///< EOI Register, WO
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LOGICAL_DESTINATION = 0x0d0, ///< Logical Destination Register, R/W
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DESTINATION_FORMAT = 0x0e0, ///< Destination Format Register, bits 0-27 RO, bits 28-31 R/W
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SPURIOUS_INTERRUPT_VECTOR = 0x0f0, ///< Spurious Interrupt Vector Register, bits 0-8 R/W, bits 9-1 R/W
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INTERRUPT_COMMAND_REGISTER_LOW = 0x300, ///< Interrupt Command Register 1, R/W
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INTERRUPT_COMMAND_REGISTER_HIGH = 0x310, ///< Interrupt Command Register 2, R/W
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TIMER_CONTROL = 0x320, ///< LAPIC timer control register, R/W
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TIMER_INITIAL_COUNTER = 0x380, ///< LAPIC timer initial counter register, R/W
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TIMER_CURRENT_COUNTER = 0x390, ///< LAPIC timer current counter register, RO
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TIMER_DIVIDE_CONFIGURATION = 0x3e0 ///< LAPIC timer divide configuration register, RW
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};
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/*! \brief Get value from APIC register
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*
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* \param idx Register Offset Index
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* \return current value of register
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*/
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Register read(Index idx);
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/*! \brief Write value to APIC register
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*
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* \param idx Register Offset Index
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* \param value value to be written into register
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*/
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void write(Index idx, Register value);
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} // namespace LAPIC
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