153 lines
4.8 KiB
C
153 lines
4.8 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* n2rng.h: Niagara2 RNG defines.
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*
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* Copyright (C) 2008 David S. Miller <davem@davemloft.net>
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*/
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#ifndef _N2RNG_H
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#define _N2RNG_H
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/* ver1 devices - n2-rng, vf-rng, kt-rng */
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#define RNG_v1_CTL_WAIT 0x0000000001fffe00ULL /* Minimum wait time */
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#define RNG_v1_CTL_WAIT_SHIFT 9
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#define RNG_v1_CTL_BYPASS 0x0000000000000100ULL /* VCO voltage source */
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#define RNG_v1_CTL_VCO 0x00000000000000c0ULL /* VCO rate control */
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#define RNG_v1_CTL_VCO_SHIFT 6
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#define RNG_v1_CTL_ASEL 0x0000000000000030ULL /* Analog MUX select */
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#define RNG_v1_CTL_ASEL_SHIFT 4
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#define RNG_v1_CTL_ASEL_NOOUT 2
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/* these are the same in v2 as in v1 */
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#define RNG_CTL_LFSR 0x0000000000000008ULL /* Use LFSR or plain shift */
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#define RNG_CTL_ES3 0x0000000000000004ULL /* Enable entropy source 3 */
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#define RNG_CTL_ES2 0x0000000000000002ULL /* Enable entropy source 2 */
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#define RNG_CTL_ES1 0x0000000000000001ULL /* Enable entropy source 1 */
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/* ver2 devices - m4-rng, m7-rng */
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#define RNG_v2_CTL_WAIT 0x0000000007fff800ULL /* Minimum wait time */
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#define RNG_v2_CTL_WAIT_SHIFT 12
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#define RNG_v2_CTL_BYPASS 0x0000000000000400ULL /* VCO voltage source */
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#define RNG_v2_CTL_VCO 0x0000000000000300ULL /* VCO rate control */
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#define RNG_v2_CTL_VCO_SHIFT 9
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#define RNG_v2_CTL_PERF 0x0000000000000180ULL /* Perf */
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#define RNG_v2_CTL_ASEL 0x0000000000000070ULL /* Analog MUX select */
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#define RNG_v2_CTL_ASEL_SHIFT 4
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#define RNG_v2_CTL_ASEL_NOOUT 7
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#define HV_FAST_RNG_GET_DIAG_CTL 0x130
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#define HV_FAST_RNG_CTL_READ 0x131
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#define HV_FAST_RNG_CTL_WRITE 0x132
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#define HV_FAST_RNG_DATA_READ_DIAG 0x133
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#define HV_FAST_RNG_DATA_READ 0x134
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#define HV_RNG_STATE_UNCONFIGURED 0
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#define HV_RNG_STATE_CONFIGURED 1
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#define HV_RNG_STATE_HEALTHCHECK 2
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#define HV_RNG_STATE_ERROR 3
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#define HV_RNG_NUM_CONTROL 4
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#ifndef __ASSEMBLY__
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extern unsigned long sun4v_rng_get_diag_ctl(void);
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extern unsigned long sun4v_rng_ctl_read_v1(unsigned long ctl_regs_ra,
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unsigned long *state,
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unsigned long *tick_delta);
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extern unsigned long sun4v_rng_ctl_read_v2(unsigned long ctl_regs_ra,
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unsigned long unit,
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unsigned long *state,
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unsigned long *tick_delta,
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unsigned long *watchdog,
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unsigned long *write_status);
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extern unsigned long sun4v_rng_ctl_write_v1(unsigned long ctl_regs_ra,
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unsigned long state,
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unsigned long write_timeout,
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unsigned long *tick_delta);
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extern unsigned long sun4v_rng_ctl_write_v2(unsigned long ctl_regs_ra,
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unsigned long state,
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unsigned long write_timeout,
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unsigned long unit);
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extern unsigned long sun4v_rng_data_read_diag_v1(unsigned long data_ra,
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unsigned long len,
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unsigned long *tick_delta);
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extern unsigned long sun4v_rng_data_read_diag_v2(unsigned long data_ra,
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unsigned long len,
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unsigned long unit,
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unsigned long *tick_delta);
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extern unsigned long sun4v_rng_data_read(unsigned long data_ra,
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unsigned long *tick_delta);
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enum n2rng_compat_id {
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N2_n2_rng,
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N2_vf_rng,
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N2_kt_rng,
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N2_m4_rng,
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N2_m7_rng,
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};
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struct n2rng_template {
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enum n2rng_compat_id id;
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int multi_capable;
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int chip_version;
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};
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struct n2rng_unit {
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u64 control[HV_RNG_NUM_CONTROL];
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};
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struct n2rng {
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struct platform_device *op;
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unsigned long flags;
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#define N2RNG_FLAG_MULTI 0x00000001 /* Multi-unit capable RNG */
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#define N2RNG_FLAG_CONTROL 0x00000002 /* Operating in control domain */
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#define N2RNG_FLAG_READY 0x00000008 /* Ready for hw-rng layer */
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#define N2RNG_FLAG_SHUTDOWN 0x00000010 /* Driver unregistering */
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#define N2RNG_FLAG_BUFFER_VALID 0x00000020 /* u32 buffer holds valid data */
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struct n2rng_template *data;
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int num_units;
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struct n2rng_unit *units;
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struct hwrng hwrng;
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u32 buffer;
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/* Registered hypervisor group API major and minor version. */
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unsigned long hvapi_major;
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unsigned long hvapi_minor;
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struct delayed_work work;
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unsigned long hv_state; /* HV_RNG_STATE_foo */
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unsigned long health_check_sec;
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unsigned long accum_cycles;
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unsigned long wd_timeo;
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#define N2RNG_HEALTH_CHECK_SEC_DEFAULT 0
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#define N2RNG_ACCUM_CYCLES_DEFAULT 2048
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#define N2RNG_WD_TIMEO_DEFAULT 0
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u64 scratch_control[HV_RNG_NUM_CONTROL];
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#define RNG_v1_SELFTEST_TICKS 38859
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#define RNG_v1_SELFTEST_VAL ((u64)0xB8820C7BD387E32C)
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#define RNG_v2_SELFTEST_TICKS 64
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#define RNG_v2_SELFTEST_VAL ((u64)0xffffffffffffffff)
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#define SELFTEST_POLY ((u64)0x231DCEE91262B8A3)
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#define SELFTEST_MATCH_GOAL 6
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#define SELFTEST_LOOPS_MAX 40000
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#define SELFTEST_BUFFER_WORDS 8
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u64 test_data;
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u64 test_control[HV_RNG_NUM_CONTROL];
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u64 test_buffer[SELFTEST_BUFFER_WORDS];
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};
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#define N2RNG_BLOCK_LIMIT 60000
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#define N2RNG_BUSY_LIMIT 100
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#define N2RNG_HCHECK_LIMIT 100
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#endif /* !(__ASSEMBLY__) */
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#endif /* _N2RNG_H */
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