58 lines
1.2 KiB
C
58 lines
1.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: James Liao <jamesjj.liao@mediatek.com>
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*/
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#ifndef __DRV_CLK_MTK_PLL_H
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#define __DRV_CLK_MTK_PLL_H
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#include <linux/types.h>
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struct clk_ops;
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struct clk_hw_onecell_data;
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struct device_node;
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struct mtk_pll_div_table {
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u32 div;
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unsigned long freq;
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};
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#define HAVE_RST_BAR BIT(0)
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#define PLL_AO BIT(1)
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struct mtk_pll_data {
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int id;
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const char *name;
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u32 reg;
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u32 pwr_reg;
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u32 en_mask;
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u32 pd_reg;
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u32 tuner_reg;
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u32 tuner_en_reg;
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u8 tuner_en_bit;
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int pd_shift;
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unsigned int flags;
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const struct clk_ops *ops;
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u32 rst_bar_mask;
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unsigned long fmin;
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unsigned long fmax;
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int pcwbits;
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int pcwibits;
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u32 pcw_reg;
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int pcw_shift;
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u32 pcw_chg_reg;
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const struct mtk_pll_div_table *div_table;
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const char *parent_name;
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u32 en_reg;
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u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
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};
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int mtk_clk_register_plls(struct device_node *node,
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const struct mtk_pll_data *plls, int num_plls,
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struct clk_hw_onecell_data *clk_data);
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void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
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struct clk_hw_onecell_data *clk_data);
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#endif /* __DRV_CLK_MTK_PLL_H */
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