275 lines
8.6 KiB
C
275 lines
8.6 KiB
C
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/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
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/* Copyright(c) 2014 - 2020 Intel Corporation */
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#ifndef _ICP_QAT_FW_H_
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#define _ICP_QAT_FW_H_
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#include <linux/types.h>
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#include "icp_qat_hw.h"
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#define QAT_FIELD_SET(flags, val, bitpos, mask) \
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{ (flags) = (((flags) & (~((mask) << (bitpos)))) | \
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(((val) & (mask)) << (bitpos))) ; }
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#define QAT_FIELD_GET(flags, bitpos, mask) \
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(((flags) >> (bitpos)) & (mask))
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#define ICP_QAT_FW_REQ_DEFAULT_SZ 128
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#define ICP_QAT_FW_RESP_DEFAULT_SZ 32
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#define ICP_QAT_FW_COMN_ONE_BYTE_SHIFT 8
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#define ICP_QAT_FW_COMN_SINGLE_BYTE_MASK 0xFF
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#define ICP_QAT_FW_NUM_LONGWORDS_1 1
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#define ICP_QAT_FW_NUM_LONGWORDS_2 2
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#define ICP_QAT_FW_NUM_LONGWORDS_3 3
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#define ICP_QAT_FW_NUM_LONGWORDS_4 4
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#define ICP_QAT_FW_NUM_LONGWORDS_5 5
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#define ICP_QAT_FW_NUM_LONGWORDS_6 6
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#define ICP_QAT_FW_NUM_LONGWORDS_7 7
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#define ICP_QAT_FW_NUM_LONGWORDS_10 10
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#define ICP_QAT_FW_NUM_LONGWORDS_13 13
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#define ICP_QAT_FW_NULL_REQ_SERV_ID 1
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enum icp_qat_fw_comn_resp_serv_id {
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ICP_QAT_FW_COMN_RESP_SERV_NULL,
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ICP_QAT_FW_COMN_RESP_SERV_CPM_FW,
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ICP_QAT_FW_COMN_RESP_SERV_DELIMITER
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};
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enum icp_qat_fw_comn_request_id {
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ICP_QAT_FW_COMN_REQ_NULL = 0,
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ICP_QAT_FW_COMN_REQ_CPM_FW_PKE = 3,
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ICP_QAT_FW_COMN_REQ_CPM_FW_LA = 4,
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ICP_QAT_FW_COMN_REQ_CPM_FW_DMA = 7,
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ICP_QAT_FW_COMN_REQ_CPM_FW_COMP = 9,
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ICP_QAT_FW_COMN_REQ_DELIMITER
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};
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struct icp_qat_fw_comn_req_hdr_cd_pars {
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union {
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struct {
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__u64 content_desc_addr;
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__u16 content_desc_resrvd1;
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__u8 content_desc_params_sz;
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__u8 content_desc_hdr_resrvd2;
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__u32 content_desc_resrvd3;
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} s;
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struct {
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__u32 serv_specif_fields[4];
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} s1;
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} u;
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};
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struct icp_qat_fw_comn_req_mid {
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__u64 opaque_data;
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__u64 src_data_addr;
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__u64 dest_data_addr;
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__u32 src_length;
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__u32 dst_length;
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};
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struct icp_qat_fw_comn_req_cd_ctrl {
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__u32 content_desc_ctrl_lw[ICP_QAT_FW_NUM_LONGWORDS_5];
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};
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struct icp_qat_fw_comn_req_hdr {
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__u8 resrvd1;
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__u8 service_cmd_id;
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__u8 service_type;
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__u8 hdr_flags;
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__u16 serv_specif_flags;
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__u16 comn_req_flags;
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};
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struct icp_qat_fw_comn_req_rqpars {
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__u32 serv_specif_rqpars_lw[ICP_QAT_FW_NUM_LONGWORDS_13];
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};
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struct icp_qat_fw_comn_req {
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struct icp_qat_fw_comn_req_hdr comn_hdr;
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struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars;
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struct icp_qat_fw_comn_req_mid comn_mid;
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struct icp_qat_fw_comn_req_rqpars serv_specif_rqpars;
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struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl;
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};
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struct icp_qat_fw_comn_error {
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__u8 xlat_err_code;
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__u8 cmp_err_code;
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};
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struct icp_qat_fw_comn_resp_hdr {
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__u8 resrvd1;
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__u8 service_id;
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__u8 response_type;
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__u8 hdr_flags;
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struct icp_qat_fw_comn_error comn_error;
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__u8 comn_status;
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__u8 cmd_id;
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};
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struct icp_qat_fw_comn_resp {
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struct icp_qat_fw_comn_resp_hdr comn_hdr;
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__u64 opaque_data;
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__u32 resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];
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};
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#define ICP_QAT_FW_COMN_REQ_FLAG_SET 1
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#define ICP_QAT_FW_COMN_REQ_FLAG_CLR 0
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#define ICP_QAT_FW_COMN_VALID_FLAG_BITPOS 7
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#define ICP_QAT_FW_COMN_VALID_FLAG_MASK 0x1
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#define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK 0x7F
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#define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \
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icp_qat_fw_comn_req_hdr_t.service_type
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#define ICP_QAT_FW_COMN_OV_SRV_TYPE_SET(icp_qat_fw_comn_req_hdr_t, val) \
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icp_qat_fw_comn_req_hdr_t.service_type = val
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#define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_GET(icp_qat_fw_comn_req_hdr_t) \
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icp_qat_fw_comn_req_hdr_t.service_cmd_id
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#define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_SET(icp_qat_fw_comn_req_hdr_t, val) \
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icp_qat_fw_comn_req_hdr_t.service_cmd_id = val
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#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_GET(hdr_t) \
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ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_t.hdr_flags)
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#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \
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ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val)
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#define ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_flags) \
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QAT_FIELD_GET(hdr_flags, \
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ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \
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ICP_QAT_FW_COMN_VALID_FLAG_MASK)
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#define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_GET(hdr_flags) \
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(hdr_flags & ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK)
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#define ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) \
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QAT_FIELD_SET((hdr_t.hdr_flags), (val), \
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ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \
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ICP_QAT_FW_COMN_VALID_FLAG_MASK)
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#define ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(valid) \
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(((valid) & ICP_QAT_FW_COMN_VALID_FLAG_MASK) << \
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ICP_QAT_FW_COMN_VALID_FLAG_BITPOS)
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#define QAT_COMN_PTR_TYPE_BITPOS 0
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#define QAT_COMN_PTR_TYPE_MASK 0x1
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#define QAT_COMN_CD_FLD_TYPE_BITPOS 1
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#define QAT_COMN_CD_FLD_TYPE_MASK 0x1
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#define QAT_COMN_PTR_TYPE_FLAT 0x0
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#define QAT_COMN_PTR_TYPE_SGL 0x1
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#define QAT_COMN_CD_FLD_TYPE_64BIT_ADR 0x0
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#define QAT_COMN_CD_FLD_TYPE_16BYTE_DATA 0x1
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#define ICP_QAT_FW_COMN_FLAGS_BUILD(cdt, ptr) \
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((((cdt) & QAT_COMN_CD_FLD_TYPE_MASK) << QAT_COMN_CD_FLD_TYPE_BITPOS) \
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| (((ptr) & QAT_COMN_PTR_TYPE_MASK) << QAT_COMN_PTR_TYPE_BITPOS))
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#define ICP_QAT_FW_COMN_PTR_TYPE_GET(flags) \
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QAT_FIELD_GET(flags, QAT_COMN_PTR_TYPE_BITPOS, QAT_COMN_PTR_TYPE_MASK)
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#define ICP_QAT_FW_COMN_CD_FLD_TYPE_GET(flags) \
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QAT_FIELD_GET(flags, QAT_COMN_CD_FLD_TYPE_BITPOS, \
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QAT_COMN_CD_FLD_TYPE_MASK)
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#define ICP_QAT_FW_COMN_PTR_TYPE_SET(flags, val) \
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QAT_FIELD_SET(flags, val, QAT_COMN_PTR_TYPE_BITPOS, \
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QAT_COMN_PTR_TYPE_MASK)
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#define ICP_QAT_FW_COMN_CD_FLD_TYPE_SET(flags, val) \
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QAT_FIELD_SET(flags, val, QAT_COMN_CD_FLD_TYPE_BITPOS, \
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QAT_COMN_CD_FLD_TYPE_MASK)
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#define ICP_QAT_FW_COMN_NEXT_ID_BITPOS 4
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#define ICP_QAT_FW_COMN_NEXT_ID_MASK 0xF0
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#define ICP_QAT_FW_COMN_CURR_ID_BITPOS 0
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#define ICP_QAT_FW_COMN_CURR_ID_MASK 0x0F
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#define ICP_QAT_FW_COMN_NEXT_ID_GET(cd_ctrl_hdr_t) \
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((((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) \
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>> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))
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#define ICP_QAT_FW_COMN_NEXT_ID_SET(cd_ctrl_hdr_t, val) \
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{ ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \
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& ICP_QAT_FW_COMN_CURR_ID_MASK) | \
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((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \
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& ICP_QAT_FW_COMN_NEXT_ID_MASK)); }
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#define ICP_QAT_FW_COMN_CURR_ID_GET(cd_ctrl_hdr_t) \
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(((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK)
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#define ICP_QAT_FW_COMN_CURR_ID_SET(cd_ctrl_hdr_t, val) \
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{ ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \
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& ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
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((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)); }
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#define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7
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#define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1
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#define QAT_COMN_RESP_PKE_STATUS_BITPOS 6
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#define QAT_COMN_RESP_PKE_STATUS_MASK 0x1
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#define QAT_COMN_RESP_CMP_STATUS_BITPOS 5
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#define QAT_COMN_RESP_CMP_STATUS_MASK 0x1
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#define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4
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#define QAT_COMN_RESP_XLAT_STATUS_MASK 0x1
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#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS 3
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#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1
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#define ICP_QAT_FW_COMN_RESP_STATUS_BUILD(crypto, comp, xlat, eolb) \
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((((crypto) & QAT_COMN_RESP_CRYPTO_STATUS_MASK) << \
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QAT_COMN_RESP_CRYPTO_STATUS_BITPOS) | \
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(((comp) & QAT_COMN_RESP_CMP_STATUS_MASK) << \
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QAT_COMN_RESP_CMP_STATUS_BITPOS) | \
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(((xlat) & QAT_COMN_RESP_XLAT_STATUS_MASK) << \
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QAT_COMN_RESP_XLAT_STATUS_BITPOS) | \
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(((eolb) & QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK) << \
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QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS))
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#define ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(status) \
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QAT_FIELD_GET(status, QAT_COMN_RESP_CRYPTO_STATUS_BITPOS, \
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QAT_COMN_RESP_CRYPTO_STATUS_MASK)
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#define ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(status) \
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QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_STATUS_BITPOS, \
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QAT_COMN_RESP_CMP_STATUS_MASK)
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#define ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(status) \
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QAT_FIELD_GET(status, QAT_COMN_RESP_XLAT_STATUS_BITPOS, \
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QAT_COMN_RESP_XLAT_STATUS_MASK)
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#define ICP_QAT_FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET(status) \
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QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS, \
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QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK)
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#define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0
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#define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1
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#define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0
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#define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_SET 1
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#define ERR_CODE_NO_ERROR 0
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#define ERR_CODE_INVALID_BLOCK_TYPE -1
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#define ERR_CODE_NO_MATCH_ONES_COMP -2
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#define ERR_CODE_TOO_MANY_LEN_OR_DIS -3
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#define ERR_CODE_INCOMPLETE_LEN -4
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#define ERR_CODE_RPT_LEN_NO_FIRST_LEN -5
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#define ERR_CODE_RPT_GT_SPEC_LEN -6
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#define ERR_CODE_INV_LIT_LEN_CODE_LEN -7
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#define ERR_CODE_INV_DIS_CODE_LEN -8
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#define ERR_CODE_INV_LIT_LEN_DIS_IN_BLK -9
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#define ERR_CODE_DIS_TOO_FAR_BACK -10
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#define ERR_CODE_OVERFLOW_ERROR -11
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#define ERR_CODE_SOFT_ERROR -12
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#define ERR_CODE_FATAL_ERROR -13
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#define ERR_CODE_SSM_ERROR -14
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#define ERR_CODE_ENDPOINT_ERROR -15
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enum icp_qat_fw_slice {
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ICP_QAT_FW_SLICE_NULL = 0,
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ICP_QAT_FW_SLICE_CIPHER = 1,
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ICP_QAT_FW_SLICE_AUTH = 2,
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ICP_QAT_FW_SLICE_DRAM_RD = 3,
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ICP_QAT_FW_SLICE_DRAM_WR = 4,
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ICP_QAT_FW_SLICE_COMP = 5,
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ICP_QAT_FW_SLICE_XLAT = 6,
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ICP_QAT_FW_SLICE_DELIMITER
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};
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#endif
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