371 lines
11 KiB
C
371 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* GPIO driver for the ACCES 104-DIO-48E series
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* Copyright (C) 2016 William Breathitt Gray
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*
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* This driver supports the following ACCES devices: 104-DIO-48E and
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* 104-DIO-24E.
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*/
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#include <linux/bits.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/irqdesc.h>
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#include <linux/isa.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include "gpio-i8255.h"
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MODULE_IMPORT_NS(I8255);
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#define DIO48E_EXTENT 16
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#define MAX_NUM_DIO48E max_num_isa_dev(DIO48E_EXTENT)
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static unsigned int base[MAX_NUM_DIO48E];
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static unsigned int num_dio48e;
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module_param_hw_array(base, uint, ioport, &num_dio48e, 0);
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MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses");
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static unsigned int irq[MAX_NUM_DIO48E];
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static unsigned int num_irq;
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module_param_hw_array(irq, uint, irq, &num_irq, 0);
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MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers");
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#define DIO48E_NUM_PPI 2
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/**
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* struct dio48e_reg - device register structure
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* @ppi: Programmable Peripheral Interface groups
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* @enable_buffer: Enable/Disable Buffer groups
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* @unused1: Unused
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* @enable_interrupt: Write: Enable Interrupt
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* Read: Disable Interrupt
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* @unused2: Unused
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* @enable_counter: Write: Enable Counter/Timer Addressing
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* Read: Disable Counter/Timer Addressing
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* @unused3: Unused
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* @clear_interrupt: Clear Interrupt
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*/
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struct dio48e_reg {
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struct i8255 ppi[DIO48E_NUM_PPI];
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u8 enable_buffer[DIO48E_NUM_PPI];
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u8 unused1;
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u8 enable_interrupt;
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u8 unused2;
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u8 enable_counter;
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u8 unused3;
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u8 clear_interrupt;
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};
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/**
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* struct dio48e_gpio - GPIO device private data structure
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* @chip: instance of the gpio_chip
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* @ppi_state: PPI device states
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* @lock: synchronization lock to prevent I/O race conditions
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* @reg: I/O address offset for the device registers
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* @irq_mask: I/O bits affected by interrupts
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*/
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struct dio48e_gpio {
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struct gpio_chip chip;
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struct i8255_state ppi_state[DIO48E_NUM_PPI];
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raw_spinlock_t lock;
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struct dio48e_reg __iomem *reg;
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unsigned char irq_mask;
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};
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static int dio48e_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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if (i8255_get_direction(dio48egpio->ppi_state, offset))
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return GPIO_LINE_DIRECTION_IN;
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return GPIO_LINE_DIRECTION_OUT;
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}
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static int dio48e_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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i8255_direction_input(dio48egpio->reg->ppi, dio48egpio->ppi_state,
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offset);
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return 0;
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}
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static int dio48e_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
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int value)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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i8255_direction_output(dio48egpio->reg->ppi, dio48egpio->ppi_state,
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offset, value);
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return 0;
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}
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static int dio48e_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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return i8255_get(dio48egpio->reg->ppi, offset);
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}
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static int dio48e_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
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unsigned long *bits)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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i8255_get_multiple(dio48egpio->reg->ppi, mask, bits, chip->ngpio);
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return 0;
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}
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static void dio48e_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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i8255_set(dio48egpio->reg->ppi, dio48egpio->ppi_state, offset, value);
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}
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static void dio48e_gpio_set_multiple(struct gpio_chip *chip,
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unsigned long *mask, unsigned long *bits)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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i8255_set_multiple(dio48egpio->reg->ppi, dio48egpio->ppi_state, mask,
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bits, chip->ngpio);
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}
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static void dio48e_irq_ack(struct irq_data *data)
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{
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}
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static void dio48e_irq_mask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned long offset = irqd_to_hwirq(data);
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unsigned long flags;
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/* only bit 3 on each respective Port C supports interrupts */
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if (offset != 19 && offset != 43)
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return;
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raw_spin_lock_irqsave(&dio48egpio->lock, flags);
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if (offset == 19)
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dio48egpio->irq_mask &= ~BIT(0);
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else
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dio48egpio->irq_mask &= ~BIT(1);
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gpiochip_disable_irq(chip, offset);
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if (!dio48egpio->irq_mask)
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/* disable interrupts */
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ioread8(&dio48egpio->reg->enable_interrupt);
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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}
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static void dio48e_irq_unmask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned long offset = irqd_to_hwirq(data);
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unsigned long flags;
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/* only bit 3 on each respective Port C supports interrupts */
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if (offset != 19 && offset != 43)
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return;
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raw_spin_lock_irqsave(&dio48egpio->lock, flags);
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if (!dio48egpio->irq_mask) {
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/* enable interrupts */
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iowrite8(0x00, &dio48egpio->reg->clear_interrupt);
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iowrite8(0x00, &dio48egpio->reg->enable_interrupt);
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}
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gpiochip_enable_irq(chip, offset);
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if (offset == 19)
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dio48egpio->irq_mask |= BIT(0);
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else
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dio48egpio->irq_mask |= BIT(1);
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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}
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static int dio48e_irq_set_type(struct irq_data *data, unsigned int flow_type)
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{
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const unsigned long offset = irqd_to_hwirq(data);
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/* only bit 3 on each respective Port C supports interrupts */
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if (offset != 19 && offset != 43)
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return -EINVAL;
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if (flow_type != IRQ_TYPE_NONE && flow_type != IRQ_TYPE_EDGE_RISING)
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return -EINVAL;
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return 0;
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}
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static const struct irq_chip dio48e_irqchip = {
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.name = "104-dio-48e",
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.irq_ack = dio48e_irq_ack,
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.irq_mask = dio48e_irq_mask,
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.irq_unmask = dio48e_irq_unmask,
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.irq_set_type = dio48e_irq_set_type,
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.flags = IRQCHIP_IMMUTABLE,
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GPIOCHIP_IRQ_RESOURCE_HELPERS,
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};
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static irqreturn_t dio48e_irq_handler(int irq, void *dev_id)
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{
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struct dio48e_gpio *const dio48egpio = dev_id;
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struct gpio_chip *const chip = &dio48egpio->chip;
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const unsigned long irq_mask = dio48egpio->irq_mask;
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unsigned long gpio;
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for_each_set_bit(gpio, &irq_mask, 2)
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generic_handle_domain_irq(chip->irq.domain,
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19 + gpio*24);
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raw_spin_lock(&dio48egpio->lock);
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iowrite8(0x00, &dio48egpio->reg->clear_interrupt);
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raw_spin_unlock(&dio48egpio->lock);
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return IRQ_HANDLED;
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}
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#define DIO48E_NGPIO 48
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static const char *dio48e_names[DIO48E_NGPIO] = {
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"PPI Group 0 Port A 0", "PPI Group 0 Port A 1", "PPI Group 0 Port A 2",
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"PPI Group 0 Port A 3", "PPI Group 0 Port A 4", "PPI Group 0 Port A 5",
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"PPI Group 0 Port A 6", "PPI Group 0 Port A 7", "PPI Group 0 Port B 0",
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"PPI Group 0 Port B 1", "PPI Group 0 Port B 2", "PPI Group 0 Port B 3",
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"PPI Group 0 Port B 4", "PPI Group 0 Port B 5", "PPI Group 0 Port B 6",
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"PPI Group 0 Port B 7", "PPI Group 0 Port C 0", "PPI Group 0 Port C 1",
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"PPI Group 0 Port C 2", "PPI Group 0 Port C 3", "PPI Group 0 Port C 4",
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"PPI Group 0 Port C 5", "PPI Group 0 Port C 6", "PPI Group 0 Port C 7",
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"PPI Group 1 Port A 0", "PPI Group 1 Port A 1", "PPI Group 1 Port A 2",
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"PPI Group 1 Port A 3", "PPI Group 1 Port A 4", "PPI Group 1 Port A 5",
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"PPI Group 1 Port A 6", "PPI Group 1 Port A 7", "PPI Group 1 Port B 0",
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"PPI Group 1 Port B 1", "PPI Group 1 Port B 2", "PPI Group 1 Port B 3",
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"PPI Group 1 Port B 4", "PPI Group 1 Port B 5", "PPI Group 1 Port B 6",
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"PPI Group 1 Port B 7", "PPI Group 1 Port C 0", "PPI Group 1 Port C 1",
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"PPI Group 1 Port C 2", "PPI Group 1 Port C 3", "PPI Group 1 Port C 4",
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"PPI Group 1 Port C 5", "PPI Group 1 Port C 6", "PPI Group 1 Port C 7"
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};
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static int dio48e_irq_init_hw(struct gpio_chip *gc)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(gc);
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/* Disable IRQ by default */
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ioread8(&dio48egpio->reg->enable_interrupt);
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return 0;
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}
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static void dio48e_init_ppi(struct i8255 __iomem *const ppi,
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struct i8255_state *const ppi_state)
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{
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const unsigned long ngpio = 24;
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const unsigned long mask = GENMASK(ngpio - 1, 0);
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const unsigned long bits = 0;
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unsigned long i;
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/* Initialize all GPIO to output 0 */
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for (i = 0; i < DIO48E_NUM_PPI; i++) {
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i8255_mode0_output(&ppi[i]);
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i8255_set_multiple(&ppi[i], &ppi_state[i], &mask, &bits, ngpio);
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}
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}
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static int dio48e_probe(struct device *dev, unsigned int id)
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{
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struct dio48e_gpio *dio48egpio;
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const char *const name = dev_name(dev);
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struct gpio_irq_chip *girq;
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int err;
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dio48egpio = devm_kzalloc(dev, sizeof(*dio48egpio), GFP_KERNEL);
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if (!dio48egpio)
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return -ENOMEM;
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if (!devm_request_region(dev, base[id], DIO48E_EXTENT, name)) {
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dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
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base[id], base[id] + DIO48E_EXTENT);
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return -EBUSY;
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}
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dio48egpio->reg = devm_ioport_map(dev, base[id], DIO48E_EXTENT);
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if (!dio48egpio->reg)
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return -ENOMEM;
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dio48egpio->chip.label = name;
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dio48egpio->chip.parent = dev;
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dio48egpio->chip.owner = THIS_MODULE;
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dio48egpio->chip.base = -1;
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dio48egpio->chip.ngpio = DIO48E_NGPIO;
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dio48egpio->chip.names = dio48e_names;
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dio48egpio->chip.get_direction = dio48e_gpio_get_direction;
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dio48egpio->chip.direction_input = dio48e_gpio_direction_input;
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dio48egpio->chip.direction_output = dio48e_gpio_direction_output;
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dio48egpio->chip.get = dio48e_gpio_get;
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dio48egpio->chip.get_multiple = dio48e_gpio_get_multiple;
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dio48egpio->chip.set = dio48e_gpio_set;
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dio48egpio->chip.set_multiple = dio48e_gpio_set_multiple;
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girq = &dio48egpio->chip.irq;
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gpio_irq_chip_set_chip(girq, &dio48e_irqchip);
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/* This will let us handle the parent IRQ in the driver */
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girq->parent_handler = NULL;
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girq->num_parents = 0;
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girq->parents = NULL;
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_edge_irq;
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|
|
girq->init_hw = dio48e_irq_init_hw;
|
||
|
|
|
||
|
|
raw_spin_lock_init(&dio48egpio->lock);
|
||
|
|
|
||
|
|
i8255_state_init(dio48egpio->ppi_state, DIO48E_NUM_PPI);
|
||
|
|
dio48e_init_ppi(dio48egpio->reg->ppi, dio48egpio->ppi_state);
|
||
|
|
|
||
|
|
err = devm_gpiochip_add_data(dev, &dio48egpio->chip, dio48egpio);
|
||
|
|
if (err) {
|
||
|
|
dev_err(dev, "GPIO registering failed (%d)\n", err);
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
err = devm_request_irq(dev, irq[id], dio48e_irq_handler, 0, name,
|
||
|
|
dio48egpio);
|
||
|
|
if (err) {
|
||
|
|
dev_err(dev, "IRQ handler registering failed (%d)\n", err);
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct isa_driver dio48e_driver = {
|
||
|
|
.probe = dio48e_probe,
|
||
|
|
.driver = {
|
||
|
|
.name = "104-dio-48e"
|
||
|
|
},
|
||
|
|
};
|
||
|
|
module_isa_driver_with_irq(dio48e_driver, num_dio48e, num_irq);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
|
||
|
|
MODULE_DESCRIPTION("ACCES 104-DIO-48E GPIO driver");
|
||
|
|
MODULE_LICENSE("GPL v2");
|