346 lines
9.1 KiB
C
346 lines
9.1 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* GPIO driver for the ACCES 104-IDIO-16 family
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* Copyright (C) 2015 William Breathitt Gray
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*
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* This driver supports the following ACCES devices: 104-IDIO-16,
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* 104-IDIO-16E, 104-IDO-16, 104-IDIO-8, 104-IDIO-8E, and 104-IDO-8.
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*/
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#include <linux/bits.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/irqdesc.h>
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#include <linux/isa.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#define IDIO_16_EXTENT 8
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#define MAX_NUM_IDIO_16 max_num_isa_dev(IDIO_16_EXTENT)
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static unsigned int base[MAX_NUM_IDIO_16];
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static unsigned int num_idio_16;
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module_param_hw_array(base, uint, ioport, &num_idio_16, 0);
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MODULE_PARM_DESC(base, "ACCES 104-IDIO-16 base addresses");
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static unsigned int irq[MAX_NUM_IDIO_16];
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static unsigned int num_irq;
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module_param_hw_array(irq, uint, irq, &num_irq, 0);
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MODULE_PARM_DESC(irq, "ACCES 104-IDIO-16 interrupt line numbers");
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/**
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* struct idio_16_reg - device registers structure
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* @out0_7: Read: N/A
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* Write: FET Drive Outputs 0-7
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* @in0_7: Read: Isolated Inputs 0-7
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* Write: Clear Interrupt
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* @irq_ctl: Read: Enable IRQ
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* Write: Disable IRQ
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* @unused: N/A
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* @out8_15: Read: N/A
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* Write: FET Drive Outputs 8-15
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* @in8_15: Read: Isolated Inputs 8-15
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* Write: N/A
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*/
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struct idio_16_reg {
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u8 out0_7;
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u8 in0_7;
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u8 irq_ctl;
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u8 unused;
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u8 out8_15;
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u8 in8_15;
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};
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/**
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* struct idio_16_gpio - GPIO device private data structure
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* @chip: instance of the gpio_chip
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* @lock: synchronization lock to prevent I/O race conditions
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* @irq_mask: I/O bits affected by interrupts
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* @reg: I/O address offset for the device registers
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* @out_state: output bits state
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*/
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struct idio_16_gpio {
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struct gpio_chip chip;
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raw_spinlock_t lock;
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unsigned long irq_mask;
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struct idio_16_reg __iomem *reg;
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unsigned int out_state;
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};
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static int idio_16_gpio_get_direction(struct gpio_chip *chip,
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unsigned int offset)
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{
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if (offset > 15)
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return GPIO_LINE_DIRECTION_IN;
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return GPIO_LINE_DIRECTION_OUT;
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}
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static int idio_16_gpio_direction_input(struct gpio_chip *chip,
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unsigned int offset)
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{
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return 0;
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}
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static int idio_16_gpio_direction_output(struct gpio_chip *chip,
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unsigned int offset, int value)
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{
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chip->set(chip, offset, value);
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return 0;
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}
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static int idio_16_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
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const unsigned int mask = BIT(offset-16);
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if (offset < 16)
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return -EINVAL;
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if (offset < 24)
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return !!(ioread8(&idio16gpio->reg->in0_7) & mask);
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return !!(ioread8(&idio16gpio->reg->in8_15) & (mask>>8));
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}
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static int idio_16_gpio_get_multiple(struct gpio_chip *chip,
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unsigned long *mask, unsigned long *bits)
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{
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struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
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*bits = 0;
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if (*mask & GENMASK(23, 16))
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*bits |= (unsigned long)ioread8(&idio16gpio->reg->in0_7) << 16;
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if (*mask & GENMASK(31, 24))
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*bits |= (unsigned long)ioread8(&idio16gpio->reg->in8_15) << 24;
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return 0;
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}
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static void idio_16_gpio_set(struct gpio_chip *chip, unsigned int offset,
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int value)
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{
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struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
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const unsigned int mask = BIT(offset);
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unsigned long flags;
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if (offset > 15)
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return;
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raw_spin_lock_irqsave(&idio16gpio->lock, flags);
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if (value)
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idio16gpio->out_state |= mask;
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else
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idio16gpio->out_state &= ~mask;
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if (offset > 7)
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iowrite8(idio16gpio->out_state >> 8, &idio16gpio->reg->out8_15);
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else
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iowrite8(idio16gpio->out_state, &idio16gpio->reg->out0_7);
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raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
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}
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static void idio_16_gpio_set_multiple(struct gpio_chip *chip,
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unsigned long *mask, unsigned long *bits)
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{
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struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
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unsigned long flags;
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raw_spin_lock_irqsave(&idio16gpio->lock, flags);
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idio16gpio->out_state &= ~*mask;
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idio16gpio->out_state |= *mask & *bits;
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if (*mask & 0xFF)
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iowrite8(idio16gpio->out_state, &idio16gpio->reg->out0_7);
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if ((*mask >> 8) & 0xFF)
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iowrite8(idio16gpio->out_state >> 8, &idio16gpio->reg->out8_15);
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raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
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}
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static void idio_16_irq_ack(struct irq_data *data)
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{
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}
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static void idio_16_irq_mask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
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const unsigned long offset = irqd_to_hwirq(data);
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unsigned long flags;
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idio16gpio->irq_mask &= ~BIT(offset);
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gpiochip_disable_irq(chip, offset);
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if (!idio16gpio->irq_mask) {
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raw_spin_lock_irqsave(&idio16gpio->lock, flags);
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iowrite8(0, &idio16gpio->reg->irq_ctl);
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raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
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}
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}
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static void idio_16_irq_unmask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
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const unsigned long offset = irqd_to_hwirq(data);
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const unsigned long prev_irq_mask = idio16gpio->irq_mask;
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unsigned long flags;
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gpiochip_enable_irq(chip, offset);
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idio16gpio->irq_mask |= BIT(offset);
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if (!prev_irq_mask) {
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raw_spin_lock_irqsave(&idio16gpio->lock, flags);
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ioread8(&idio16gpio->reg->irq_ctl);
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raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
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}
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}
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static int idio_16_irq_set_type(struct irq_data *data, unsigned int flow_type)
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{
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/* The only valid irq types are none and both-edges */
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if (flow_type != IRQ_TYPE_NONE &&
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(flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
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return -EINVAL;
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return 0;
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}
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static const struct irq_chip idio_16_irqchip = {
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.name = "104-idio-16",
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.irq_ack = idio_16_irq_ack,
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.irq_mask = idio_16_irq_mask,
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.irq_unmask = idio_16_irq_unmask,
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.irq_set_type = idio_16_irq_set_type,
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.flags = IRQCHIP_IMMUTABLE,
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GPIOCHIP_IRQ_RESOURCE_HELPERS,
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};
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static irqreturn_t idio_16_irq_handler(int irq, void *dev_id)
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{
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struct idio_16_gpio *const idio16gpio = dev_id;
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struct gpio_chip *const chip = &idio16gpio->chip;
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int gpio;
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for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)
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generic_handle_domain_irq(chip->irq.domain, gpio);
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raw_spin_lock(&idio16gpio->lock);
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iowrite8(0, &idio16gpio->reg->in0_7);
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raw_spin_unlock(&idio16gpio->lock);
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return IRQ_HANDLED;
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}
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#define IDIO_16_NGPIO 32
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static const char *idio_16_names[IDIO_16_NGPIO] = {
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"OUT0", "OUT1", "OUT2", "OUT3", "OUT4", "OUT5", "OUT6", "OUT7",
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"OUT8", "OUT9", "OUT10", "OUT11", "OUT12", "OUT13", "OUT14", "OUT15",
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"IIN0", "IIN1", "IIN2", "IIN3", "IIN4", "IIN5", "IIN6", "IIN7",
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"IIN8", "IIN9", "IIN10", "IIN11", "IIN12", "IIN13", "IIN14", "IIN15"
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};
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static int idio_16_irq_init_hw(struct gpio_chip *gc)
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{
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struct idio_16_gpio *const idio16gpio = gpiochip_get_data(gc);
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/* Disable IRQ by default */
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iowrite8(0, &idio16gpio->reg->irq_ctl);
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iowrite8(0, &idio16gpio->reg->in0_7);
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return 0;
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}
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static int idio_16_probe(struct device *dev, unsigned int id)
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{
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struct idio_16_gpio *idio16gpio;
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const char *const name = dev_name(dev);
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struct gpio_irq_chip *girq;
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int err;
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idio16gpio = devm_kzalloc(dev, sizeof(*idio16gpio), GFP_KERNEL);
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if (!idio16gpio)
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return -ENOMEM;
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if (!devm_request_region(dev, base[id], IDIO_16_EXTENT, name)) {
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dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
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base[id], base[id] + IDIO_16_EXTENT);
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return -EBUSY;
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}
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idio16gpio->reg = devm_ioport_map(dev, base[id], IDIO_16_EXTENT);
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if (!idio16gpio->reg)
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return -ENOMEM;
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idio16gpio->chip.label = name;
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idio16gpio->chip.parent = dev;
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idio16gpio->chip.owner = THIS_MODULE;
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idio16gpio->chip.base = -1;
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idio16gpio->chip.ngpio = IDIO_16_NGPIO;
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idio16gpio->chip.names = idio_16_names;
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idio16gpio->chip.get_direction = idio_16_gpio_get_direction;
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idio16gpio->chip.direction_input = idio_16_gpio_direction_input;
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idio16gpio->chip.direction_output = idio_16_gpio_direction_output;
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idio16gpio->chip.get = idio_16_gpio_get;
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idio16gpio->chip.get_multiple = idio_16_gpio_get_multiple;
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idio16gpio->chip.set = idio_16_gpio_set;
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idio16gpio->chip.set_multiple = idio_16_gpio_set_multiple;
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idio16gpio->out_state = 0xFFFF;
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girq = &idio16gpio->chip.irq;
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gpio_irq_chip_set_chip(girq, &idio_16_irqchip);
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/* This will let us handle the parent IRQ in the driver */
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girq->parent_handler = NULL;
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girq->num_parents = 0;
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girq->parents = NULL;
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_edge_irq;
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girq->init_hw = idio_16_irq_init_hw;
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raw_spin_lock_init(&idio16gpio->lock);
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err = devm_gpiochip_add_data(dev, &idio16gpio->chip, idio16gpio);
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if (err) {
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dev_err(dev, "GPIO registering failed (%d)\n", err);
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return err;
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}
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err = devm_request_irq(dev, irq[id], idio_16_irq_handler, 0, name,
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idio16gpio);
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if (err) {
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dev_err(dev, "IRQ handler registering failed (%d)\n", err);
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return err;
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}
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return 0;
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}
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static struct isa_driver idio_16_driver = {
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.probe = idio_16_probe,
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.driver = {
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.name = "104-idio-16"
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},
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};
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module_isa_driver_with_irq(idio_16_driver, num_idio_16, num_irq);
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MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
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MODULE_DESCRIPTION("ACCES 104-IDIO-16 GPIO driver");
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MODULE_LICENSE("GPL v2");
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