300 lines
9.6 KiB
C
300 lines
9.6 KiB
C
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/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <linux/module.h>
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#include <linux/fdtable.h>
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#include <linux/uaccess.h>
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#include <linux/firmware.h>
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#include "amdgpu.h"
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#include "amdgpu_amdkfd.h"
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#include "amdgpu_amdkfd_arcturus.h"
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#include "sdma0/sdma0_4_2_2_offset.h"
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#include "sdma0/sdma0_4_2_2_sh_mask.h"
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#include "sdma1/sdma1_4_2_2_offset.h"
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#include "sdma1/sdma1_4_2_2_sh_mask.h"
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#include "sdma2/sdma2_4_2_2_offset.h"
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#include "sdma2/sdma2_4_2_2_sh_mask.h"
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#include "sdma3/sdma3_4_2_2_offset.h"
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#include "sdma3/sdma3_4_2_2_sh_mask.h"
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#include "sdma4/sdma4_4_2_2_offset.h"
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#include "sdma4/sdma4_4_2_2_sh_mask.h"
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#include "sdma5/sdma5_4_2_2_offset.h"
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#include "sdma5/sdma5_4_2_2_sh_mask.h"
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#include "sdma6/sdma6_4_2_2_offset.h"
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#include "sdma6/sdma6_4_2_2_sh_mask.h"
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#include "sdma7/sdma7_4_2_2_offset.h"
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#include "sdma7/sdma7_4_2_2_sh_mask.h"
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#include "v9_structs.h"
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#include "soc15.h"
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#include "soc15d.h"
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#include "amdgpu_amdkfd_gfx_v9.h"
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#include "gfxhub_v1_0.h"
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#include "mmhub_v9_4.h"
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#define HQD_N_REGS 56
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#define DUMP_REG(addr) do { \
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if (WARN_ON_ONCE(i >= HQD_N_REGS)) \
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break; \
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(*dump)[i][0] = (addr) << 2; \
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(*dump)[i++][1] = RREG32(addr); \
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} while (0)
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static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd)
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{
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return (struct v9_sdma_mqd *)mqd;
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}
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static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
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unsigned int engine_id,
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unsigned int queue_id)
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{
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uint32_t sdma_engine_reg_base = 0;
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uint32_t sdma_rlc_reg_offset;
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switch (engine_id) {
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default:
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dev_warn(adev->dev,
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"Invalid sdma engine id (%d), using engine id 0\n",
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engine_id);
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fallthrough;
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case 0:
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sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
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mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
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break;
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case 1:
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sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,
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mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL;
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break;
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case 2:
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sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA2, 0,
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mmSDMA2_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL;
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break;
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case 3:
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sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA3, 0,
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mmSDMA3_RLC0_RB_CNTL) - mmSDMA3_RLC0_RB_CNTL;
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break;
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case 4:
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sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA4, 0,
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mmSDMA4_RLC0_RB_CNTL) - mmSDMA4_RLC0_RB_CNTL;
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break;
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case 5:
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sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA5, 0,
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mmSDMA5_RLC0_RB_CNTL) - mmSDMA5_RLC0_RB_CNTL;
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break;
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case 6:
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sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA6, 0,
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mmSDMA6_RLC0_RB_CNTL) - mmSDMA6_RLC0_RB_CNTL;
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break;
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case 7:
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sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA7, 0,
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mmSDMA7_RLC0_RB_CNTL) - mmSDMA7_RLC0_RB_CNTL;
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break;
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}
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sdma_rlc_reg_offset = sdma_engine_reg_base
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+ queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
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pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
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queue_id, sdma_rlc_reg_offset);
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return sdma_rlc_reg_offset;
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}
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int kgd_arcturus_hqd_sdma_load(struct amdgpu_device *adev, void *mqd,
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uint32_t __user *wptr, struct mm_struct *mm)
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{
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struct v9_sdma_mqd *m;
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uint32_t sdma_rlc_reg_offset;
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unsigned long end_jiffies;
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uint32_t data;
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uint64_t data64;
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uint64_t __user *wptr64 = (uint64_t __user *)wptr;
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m = get_sdma_mqd(mqd);
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sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
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m->sdma_queue_id);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
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m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
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end_jiffies = msecs_to_jiffies(2000) + jiffies;
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while (true) {
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data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
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if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
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break;
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if (time_after(jiffies, end_jiffies)) {
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pr_err("SDMA RLC not idle in %s\n", __func__);
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return -ETIME;
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}
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usleep_range(500, 1000);
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}
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
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m->sdmax_rlcx_doorbell_offset);
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data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
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ENABLE, 1);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
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m->sdmax_rlcx_rb_rptr);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
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m->sdmax_rlcx_rb_rptr_hi);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
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if (read_user_wptr(mm, wptr64, data64)) {
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
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lower_32_bits(data64));
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
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upper_32_bits(data64));
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} else {
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
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m->sdmax_rlcx_rb_rptr);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
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m->sdmax_rlcx_rb_rptr_hi);
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}
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
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m->sdmax_rlcx_rb_base_hi);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
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m->sdmax_rlcx_rb_rptr_addr_lo);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
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m->sdmax_rlcx_rb_rptr_addr_hi);
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data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
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RB_ENABLE, 1);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
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return 0;
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}
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int kgd_arcturus_hqd_sdma_dump(struct amdgpu_device *adev,
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uint32_t engine_id, uint32_t queue_id,
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uint32_t (**dump)[2], uint32_t *n_regs)
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{
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uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
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engine_id, queue_id);
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uint32_t i = 0, reg;
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#undef HQD_N_REGS
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#define HQD_N_REGS (19+6+7+10)
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*dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
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if (*dump == NULL)
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return -ENOMEM;
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for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
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DUMP_REG(sdma_rlc_reg_offset + reg);
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for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
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DUMP_REG(sdma_rlc_reg_offset + reg);
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for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
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reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
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DUMP_REG(sdma_rlc_reg_offset + reg);
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for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
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reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
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DUMP_REG(sdma_rlc_reg_offset + reg);
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WARN_ON_ONCE(i != HQD_N_REGS);
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*n_regs = i;
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return 0;
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}
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bool kgd_arcturus_hqd_sdma_is_occupied(struct amdgpu_device *adev,
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void *mqd)
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{
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struct v9_sdma_mqd *m;
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uint32_t sdma_rlc_reg_offset;
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uint32_t sdma_rlc_rb_cntl;
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m = get_sdma_mqd(mqd);
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sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
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m->sdma_queue_id);
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sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
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if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
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return true;
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return false;
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}
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int kgd_arcturus_hqd_sdma_destroy(struct amdgpu_device *adev, void *mqd,
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unsigned int utimeout)
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{
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struct v9_sdma_mqd *m;
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uint32_t sdma_rlc_reg_offset;
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uint32_t temp;
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unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
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m = get_sdma_mqd(mqd);
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sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
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m->sdma_queue_id);
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temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
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temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
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while (true) {
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temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
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if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
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break;
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if (time_after(jiffies, end_jiffies)) {
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pr_err("SDMA RLC not idle in %s\n", __func__);
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return -ETIME;
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}
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usleep_range(500, 1000);
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}
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
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RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
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SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
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m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
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m->sdmax_rlcx_rb_rptr_hi =
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RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);
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return 0;
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}
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const struct kfd2kgd_calls arcturus_kfd2kgd = {
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.program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings,
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.set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping,
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.init_interrupts = kgd_gfx_v9_init_interrupts,
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.hqd_load = kgd_gfx_v9_hqd_load,
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.hiq_mqd_load = kgd_gfx_v9_hiq_mqd_load,
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.hqd_sdma_load = kgd_arcturus_hqd_sdma_load,
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.hqd_dump = kgd_gfx_v9_hqd_dump,
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.hqd_sdma_dump = kgd_arcturus_hqd_sdma_dump,
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.hqd_is_occupied = kgd_gfx_v9_hqd_is_occupied,
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.hqd_sdma_is_occupied = kgd_arcturus_hqd_sdma_is_occupied,
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.hqd_destroy = kgd_gfx_v9_hqd_destroy,
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.hqd_sdma_destroy = kgd_arcturus_hqd_sdma_destroy,
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.wave_control_execute = kgd_gfx_v9_wave_control_execute,
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.get_atc_vmid_pasid_mapping_info =
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||
|
|
kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
|
||
|
|
.set_vm_context_page_table_base =
|
||
|
|
kgd_gfx_v9_set_vm_context_page_table_base,
|
||
|
|
.get_cu_occupancy = kgd_gfx_v9_get_cu_occupancy,
|
||
|
|
.program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings
|
||
|
|
};
|