393 lines
11 KiB
C
393 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* adv7511_cec.c - Analog Devices ADV7511/33 cec driver
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*
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* Copyright 2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
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*/
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <media/cec.h>
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#include "adv7511.h"
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static const u8 ADV7511_REG_CEC_RX_FRAME_HDR[] = {
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ADV7511_REG_CEC_RX1_FRAME_HDR,
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ADV7511_REG_CEC_RX2_FRAME_HDR,
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ADV7511_REG_CEC_RX3_FRAME_HDR,
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};
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static const u8 ADV7511_REG_CEC_RX_FRAME_LEN[] = {
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ADV7511_REG_CEC_RX1_FRAME_LEN,
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ADV7511_REG_CEC_RX2_FRAME_LEN,
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ADV7511_REG_CEC_RX3_FRAME_LEN,
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};
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#define ADV7511_INT1_CEC_MASK \
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(ADV7511_INT1_CEC_TX_READY | ADV7511_INT1_CEC_TX_ARBIT_LOST | \
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ADV7511_INT1_CEC_TX_RETRY_TIMEOUT | ADV7511_INT1_CEC_RX_READY1 | \
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ADV7511_INT1_CEC_RX_READY2 | ADV7511_INT1_CEC_RX_READY3)
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static void adv_cec_tx_raw_status(struct adv7511 *adv7511, u8 tx_raw_status)
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{
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unsigned int offset = adv7511->reg_cec_offset;
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unsigned int val;
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if (regmap_read(adv7511->regmap_cec,
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ADV7511_REG_CEC_TX_ENABLE + offset, &val))
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return;
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if ((val & 0x01) == 0)
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return;
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if (tx_raw_status & ADV7511_INT1_CEC_TX_ARBIT_LOST) {
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cec_transmit_attempt_done(adv7511->cec_adap,
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CEC_TX_STATUS_ARB_LOST);
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return;
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}
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if (tx_raw_status & ADV7511_INT1_CEC_TX_RETRY_TIMEOUT) {
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u8 status;
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u8 err_cnt = 0;
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u8 nack_cnt = 0;
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u8 low_drive_cnt = 0;
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unsigned int cnt;
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/*
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* We set this status bit since this hardware performs
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* retransmissions.
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*/
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status = CEC_TX_STATUS_MAX_RETRIES;
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if (regmap_read(adv7511->regmap_cec,
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ADV7511_REG_CEC_TX_LOW_DRV_CNT + offset, &cnt)) {
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err_cnt = 1;
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status |= CEC_TX_STATUS_ERROR;
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} else {
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nack_cnt = cnt & 0xf;
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if (nack_cnt)
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status |= CEC_TX_STATUS_NACK;
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low_drive_cnt = cnt >> 4;
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if (low_drive_cnt)
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status |= CEC_TX_STATUS_LOW_DRIVE;
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}
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cec_transmit_done(adv7511->cec_adap, status,
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0, nack_cnt, low_drive_cnt, err_cnt);
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return;
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}
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if (tx_raw_status & ADV7511_INT1_CEC_TX_READY) {
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cec_transmit_attempt_done(adv7511->cec_adap, CEC_TX_STATUS_OK);
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return;
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}
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}
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static void adv7511_cec_rx(struct adv7511 *adv7511, int rx_buf)
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{
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unsigned int offset = adv7511->reg_cec_offset;
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struct cec_msg msg = {};
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unsigned int len;
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unsigned int val;
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u8 i;
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if (regmap_read(adv7511->regmap_cec,
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ADV7511_REG_CEC_RX_FRAME_LEN[rx_buf] + offset, &len))
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return;
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msg.len = len & 0x1f;
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if (msg.len > 16)
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msg.len = 16;
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if (!msg.len)
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return;
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for (i = 0; i < msg.len; i++) {
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regmap_read(adv7511->regmap_cec,
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i + ADV7511_REG_CEC_RX_FRAME_HDR[rx_buf] + offset,
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&val);
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msg.msg[i] = val;
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}
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/* Toggle RX Ready Clear bit to re-enable this RX buffer */
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regmap_update_bits(adv7511->regmap_cec,
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ADV7511_REG_CEC_RX_BUFFERS + offset, BIT(rx_buf),
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BIT(rx_buf));
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regmap_update_bits(adv7511->regmap_cec,
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ADV7511_REG_CEC_RX_BUFFERS + offset, BIT(rx_buf), 0);
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cec_received_msg(adv7511->cec_adap, &msg);
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}
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void adv7511_cec_irq_process(struct adv7511 *adv7511, unsigned int irq1)
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{
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unsigned int offset = adv7511->reg_cec_offset;
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const u32 irq_tx_mask = ADV7511_INT1_CEC_TX_READY |
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ADV7511_INT1_CEC_TX_ARBIT_LOST |
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ADV7511_INT1_CEC_TX_RETRY_TIMEOUT;
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const u32 irq_rx_mask = ADV7511_INT1_CEC_RX_READY1 |
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ADV7511_INT1_CEC_RX_READY2 |
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ADV7511_INT1_CEC_RX_READY3;
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unsigned int rx_status;
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int rx_order[3] = { -1, -1, -1 };
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int i;
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if (irq1 & irq_tx_mask)
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adv_cec_tx_raw_status(adv7511, irq1);
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if (!(irq1 & irq_rx_mask))
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return;
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if (regmap_read(adv7511->regmap_cec,
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ADV7511_REG_CEC_RX_STATUS + offset, &rx_status))
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return;
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/*
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* ADV7511_REG_CEC_RX_STATUS[5:0] contains the reception order of RX
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* buffers 0, 1, and 2 in bits [1:0], [3:2], and [5:4] respectively.
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* The values are to be interpreted as follows:
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*
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* 0 = buffer unused
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* 1 = buffer contains oldest received frame (if applicable)
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* 2 = buffer contains second oldest received frame (if applicable)
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* 3 = buffer contains third oldest received frame (if applicable)
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*
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* Fill rx_order with the sequence of RX buffer indices to
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* read from in order, where -1 indicates that there are no
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* more buffers to process.
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*/
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for (i = 0; i < 3; i++) {
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unsigned int timestamp = (rx_status >> (2 * i)) & 0x3;
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if (timestamp)
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rx_order[timestamp - 1] = i;
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}
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/* Read CEC RX buffers in the appropriate order as prescribed above */
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for (i = 0; i < 3; i++) {
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int rx_buf = rx_order[i];
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if (rx_buf < 0)
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break;
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adv7511_cec_rx(adv7511, rx_buf);
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}
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}
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static int adv7511_cec_adap_enable(struct cec_adapter *adap, bool enable)
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{
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struct adv7511 *adv7511 = cec_get_drvdata(adap);
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unsigned int offset = adv7511->reg_cec_offset;
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if (adv7511->i2c_cec == NULL)
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return -EIO;
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if (!adv7511->cec_enabled_adap && enable) {
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/* power up cec section */
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regmap_update_bits(adv7511->regmap_cec,
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ADV7511_REG_CEC_CLK_DIV + offset,
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0x03, 0x01);
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/* non-legacy mode and clear all rx buffers */
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regmap_write(adv7511->regmap_cec,
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ADV7511_REG_CEC_RX_BUFFERS + offset, 0x0f);
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regmap_write(adv7511->regmap_cec,
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ADV7511_REG_CEC_RX_BUFFERS + offset, 0x08);
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/* initially disable tx */
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regmap_update_bits(adv7511->regmap_cec,
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ADV7511_REG_CEC_TX_ENABLE + offset, 1, 0);
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/* enabled irqs: */
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/* tx: ready */
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/* tx: arbitration lost */
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/* tx: retry timeout */
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/* rx: ready 1-3 */
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regmap_update_bits(adv7511->regmap,
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ADV7511_REG_INT_ENABLE(1), 0x3f,
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ADV7511_INT1_CEC_MASK);
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} else if (adv7511->cec_enabled_adap && !enable) {
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regmap_update_bits(adv7511->regmap,
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ADV7511_REG_INT_ENABLE(1), 0x3f, 0);
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/* disable address mask 1-3 */
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regmap_update_bits(adv7511->regmap_cec,
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ADV7511_REG_CEC_LOG_ADDR_MASK + offset,
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0x70, 0x00);
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/* power down cec section */
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regmap_update_bits(adv7511->regmap_cec,
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ADV7511_REG_CEC_CLK_DIV + offset,
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0x03, 0x00);
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adv7511->cec_valid_addrs = 0;
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}
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adv7511->cec_enabled_adap = enable;
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return 0;
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}
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static int adv7511_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
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{
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struct adv7511 *adv7511 = cec_get_drvdata(adap);
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unsigned int offset = adv7511->reg_cec_offset;
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unsigned int i, free_idx = ADV7511_MAX_ADDRS;
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if (!adv7511->cec_enabled_adap)
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return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
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if (addr == CEC_LOG_ADDR_INVALID) {
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regmap_update_bits(adv7511->regmap_cec,
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ADV7511_REG_CEC_LOG_ADDR_MASK + offset,
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0x70, 0);
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adv7511->cec_valid_addrs = 0;
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return 0;
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}
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for (i = 0; i < ADV7511_MAX_ADDRS; i++) {
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bool is_valid = adv7511->cec_valid_addrs & (1 << i);
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if (free_idx == ADV7511_MAX_ADDRS && !is_valid)
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free_idx = i;
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if (is_valid && adv7511->cec_addr[i] == addr)
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return 0;
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}
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if (i == ADV7511_MAX_ADDRS) {
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i = free_idx;
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if (i == ADV7511_MAX_ADDRS)
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return -ENXIO;
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}
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adv7511->cec_addr[i] = addr;
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adv7511->cec_valid_addrs |= 1 << i;
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switch (i) {
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case 0:
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/* enable address mask 0 */
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regmap_update_bits(adv7511->regmap_cec,
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ADV7511_REG_CEC_LOG_ADDR_MASK + offset,
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0x10, 0x10);
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/* set address for mask 0 */
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regmap_update_bits(adv7511->regmap_cec,
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ADV7511_REG_CEC_LOG_ADDR_0_1 + offset,
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0x0f, addr);
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break;
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case 1:
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/* enable address mask 1 */
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regmap_update_bits(adv7511->regmap_cec,
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ADV7511_REG_CEC_LOG_ADDR_MASK + offset,
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0x20, 0x20);
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/* set address for mask 1 */
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regmap_update_bits(adv7511->regmap_cec,
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ADV7511_REG_CEC_LOG_ADDR_0_1 + offset,
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0xf0, addr << 4);
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break;
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case 2:
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/* enable address mask 2 */
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regmap_update_bits(adv7511->regmap_cec,
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ADV7511_REG_CEC_LOG_ADDR_MASK + offset,
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0x40, 0x40);
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/* set address for mask 1 */
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regmap_update_bits(adv7511->regmap_cec,
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ADV7511_REG_CEC_LOG_ADDR_2 + offset,
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0x0f, addr);
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break;
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}
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return 0;
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}
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static int adv7511_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
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u32 signal_free_time, struct cec_msg *msg)
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{
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struct adv7511 *adv7511 = cec_get_drvdata(adap);
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unsigned int offset = adv7511->reg_cec_offset;
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u8 len = msg->len;
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unsigned int i;
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/*
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* The number of retries is the number of attempts - 1, but retry
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* at least once. It's not clear if a value of 0 is allowed, so
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* let's do at least one retry.
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*/
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regmap_update_bits(adv7511->regmap_cec,
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ADV7511_REG_CEC_TX_RETRY + offset,
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0x70, max(1, attempts - 1) << 4);
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/* blocking, clear cec tx irq status */
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regmap_update_bits(adv7511->regmap, ADV7511_REG_INT(1), 0x38, 0x38);
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/* write data */
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for (i = 0; i < len; i++)
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regmap_write(adv7511->regmap_cec,
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i + ADV7511_REG_CEC_TX_FRAME_HDR + offset,
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msg->msg[i]);
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/* set length (data + header) */
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regmap_write(adv7511->regmap_cec,
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ADV7511_REG_CEC_TX_FRAME_LEN + offset, len);
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/* start transmit, enable tx */
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regmap_write(adv7511->regmap_cec,
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ADV7511_REG_CEC_TX_ENABLE + offset, 0x01);
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return 0;
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}
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static const struct cec_adap_ops adv7511_cec_adap_ops = {
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.adap_enable = adv7511_cec_adap_enable,
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.adap_log_addr = adv7511_cec_adap_log_addr,
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.adap_transmit = adv7511_cec_adap_transmit,
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};
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static int adv7511_cec_parse_dt(struct device *dev, struct adv7511 *adv7511)
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{
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adv7511->cec_clk = devm_clk_get(dev, "cec");
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if (IS_ERR(adv7511->cec_clk)) {
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int ret = PTR_ERR(adv7511->cec_clk);
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adv7511->cec_clk = NULL;
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
clk_prepare_enable(adv7511->cec_clk);
|
||
|
|
adv7511->cec_clk_freq = clk_get_rate(adv7511->cec_clk);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511)
|
||
|
|
{
|
||
|
|
unsigned int offset = adv7511->reg_cec_offset;
|
||
|
|
int ret = adv7511_cec_parse_dt(dev, adv7511);
|
||
|
|
|
||
|
|
if (ret)
|
||
|
|
goto err_cec_parse_dt;
|
||
|
|
|
||
|
|
adv7511->cec_adap = cec_allocate_adapter(&adv7511_cec_adap_ops,
|
||
|
|
adv7511, dev_name(dev), CEC_CAP_DEFAULTS, ADV7511_MAX_ADDRS);
|
||
|
|
if (IS_ERR(adv7511->cec_adap)) {
|
||
|
|
ret = PTR_ERR(adv7511->cec_adap);
|
||
|
|
goto err_cec_alloc;
|
||
|
|
}
|
||
|
|
|
||
|
|
regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL, 0);
|
||
|
|
/* cec soft reset */
|
||
|
|
regmap_write(adv7511->regmap_cec,
|
||
|
|
ADV7511_REG_CEC_SOFT_RESET + offset, 0x01);
|
||
|
|
regmap_write(adv7511->regmap_cec,
|
||
|
|
ADV7511_REG_CEC_SOFT_RESET + offset, 0x00);
|
||
|
|
|
||
|
|
/* non-legacy mode - use all three RX buffers */
|
||
|
|
regmap_write(adv7511->regmap_cec,
|
||
|
|
ADV7511_REG_CEC_RX_BUFFERS + offset, 0x08);
|
||
|
|
|
||
|
|
regmap_write(adv7511->regmap_cec,
|
||
|
|
ADV7511_REG_CEC_CLK_DIV + offset,
|
||
|
|
((adv7511->cec_clk_freq / 750000) - 1) << 2);
|
||
|
|
|
||
|
|
ret = cec_register_adapter(adv7511->cec_adap, dev);
|
||
|
|
if (ret)
|
||
|
|
goto err_cec_register;
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
err_cec_register:
|
||
|
|
cec_delete_adapter(adv7511->cec_adap);
|
||
|
|
adv7511->cec_adap = NULL;
|
||
|
|
err_cec_alloc:
|
||
|
|
dev_info(dev, "Initializing CEC failed with error %d, disabling CEC\n",
|
||
|
|
ret);
|
||
|
|
err_cec_parse_dt:
|
||
|
|
regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL,
|
||
|
|
ADV7511_CEC_CTRL_POWER_DOWN);
|
||
|
|
return ret == -EPROBE_DEFER ? ret : 0;
|
||
|
|
}
|