448 lines
13 KiB
C
448 lines
13 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2010 Matt Turner.
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* Copyright 2012 Red Hat
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*
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* Authors: Matthew Garrett
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* Matt Turner
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* Dave Airlie
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*/
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#ifndef __MGAG200_DRV_H__
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#define __MGAG200_DRV_H__
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#include <linux/i2c-algo-bit.h>
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#include <linux/i2c.h>
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#include <video/vga.h>
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#include <drm/drm_connector.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_encoder.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_gem.h>
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#include <drm/drm_gem_shmem_helper.h>
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#include <drm/drm_plane.h>
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#include "mgag200_reg.h"
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#define DRIVER_AUTHOR "Matthew Garrett"
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#define DRIVER_NAME "mgag200"
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#define DRIVER_DESC "MGA G200 SE"
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#define DRIVER_DATE "20110418"
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#define DRIVER_MAJOR 1
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#define DRIVER_MINOR 0
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#define DRIVER_PATCHLEVEL 0
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#define RREG8(reg) ioread8(((void __iomem *)mdev->rmmio) + (reg))
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#define WREG8(reg, v) iowrite8(v, ((void __iomem *)mdev->rmmio) + (reg))
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#define RREG32(reg) ioread32(((void __iomem *)mdev->rmmio) + (reg))
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#define WREG32(reg, v) iowrite32(v, ((void __iomem *)mdev->rmmio) + (reg))
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#define MGA_BIOS_OFFSET 0x7ffc
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#define ATTR_INDEX 0x1fc0
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#define ATTR_DATA 0x1fc1
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#define WREG_MISC(v) \
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WREG8(MGA_MISC_OUT, v)
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#define RREG_MISC(v) \
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((v) = RREG8(MGA_MISC_IN))
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#define WREG_MISC_MASKED(v, mask) \
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do { \
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u8 misc_; \
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u8 mask_ = (mask); \
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RREG_MISC(misc_); \
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misc_ &= ~mask_; \
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misc_ |= ((v) & mask_); \
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WREG_MISC(misc_); \
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} while (0)
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#define WREG_ATTR(reg, v) \
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do { \
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RREG8(0x1fda); \
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WREG8(ATTR_INDEX, reg); \
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WREG8(ATTR_DATA, v); \
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} while (0) \
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#define RREG_SEQ(reg, v) \
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do { \
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WREG8(MGAREG_SEQ_INDEX, reg); \
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v = RREG8(MGAREG_SEQ_DATA); \
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} while (0) \
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#define WREG_SEQ(reg, v) \
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do { \
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WREG8(MGAREG_SEQ_INDEX, reg); \
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WREG8(MGAREG_SEQ_DATA, v); \
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} while (0) \
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#define RREG_CRT(reg, v) \
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do { \
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WREG8(MGAREG_CRTC_INDEX, reg); \
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v = RREG8(MGAREG_CRTC_DATA); \
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} while (0) \
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#define WREG_CRT(reg, v) \
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do { \
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WREG8(MGAREG_CRTC_INDEX, reg); \
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WREG8(MGAREG_CRTC_DATA, v); \
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} while (0) \
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#define RREG_ECRT(reg, v) \
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do { \
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WREG8(MGAREG_CRTCEXT_INDEX, reg); \
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v = RREG8(MGAREG_CRTCEXT_DATA); \
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} while (0) \
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#define WREG_ECRT(reg, v) \
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do { \
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WREG8(MGAREG_CRTCEXT_INDEX, reg); \
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WREG8(MGAREG_CRTCEXT_DATA, v); \
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} while (0) \
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#define GFX_INDEX 0x1fce
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#define GFX_DATA 0x1fcf
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#define WREG_GFX(reg, v) \
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do { \
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WREG8(GFX_INDEX, reg); \
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WREG8(GFX_DATA, v); \
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} while (0) \
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#define DAC_INDEX 0x3c00
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#define DAC_DATA 0x3c0a
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#define WREG_DAC(reg, v) \
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do { \
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WREG8(DAC_INDEX, reg); \
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WREG8(DAC_DATA, v); \
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} while (0) \
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#define MGA_MISC_OUT 0x1fc2
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#define MGA_MISC_IN 0x1fcc
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/*
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* TODO: This is a pretty large set of default values for all kinds of
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* settings. It should be split and set in the various DRM helpers,
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* such as the CRTC reset or atomic_enable helpers. The PLL values
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* probably belong to each model's PLL code.
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*/
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#define MGAG200_DAC_DEFAULT(xvrefctrl, xpixclkctrl, xmiscctrl, xsyspllm, xsysplln, xsyspllp) \
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/* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0, \
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/* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0, \
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/* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0, \
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/* 0x18: */ (xvrefctrl), \
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/* 0x19: */ 0, \
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/* 0x1a: */ (xpixclkctrl), \
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/* 0x1b: */ 0xff, 0xbf, 0x20, \
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/* 0x1e: */ (xmiscctrl), \
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/* 0x1f: */ 0x20, \
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/* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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/* 0x28: */ 0x00, 0x00, 0x00, 0x00, \
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/* 0x2c: */ (xsyspllm), \
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/* 0x2d: */ (xsysplln), \
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/* 0x2e: */ (xsyspllp), \
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/* 0x2f: */ 0x40, \
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/* 0x30: */ 0x00, 0xb0, 0x00, 0xc2, 0x34, 0x14, 0x02, 0x83, \
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/* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3a, \
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/* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0, \
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/* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0 \
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#define MGAG200_LUT_SIZE 256
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#define MGAG200_MAX_FB_HEIGHT 4096
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#define MGAG200_MAX_FB_WIDTH 4096
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struct mga_device;
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/*
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* Stores parameters for programming the PLLs
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*
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* Fref: reference frequency (A: 25.175 Mhz, B: 28.361, C: XX Mhz)
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* Fo: output frequency
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* Fvco = Fref * (N / M)
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* Fo = Fvco / P
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*
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* S = [0..3]
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*/
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struct mgag200_pll_values {
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unsigned int m;
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unsigned int n;
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unsigned int p;
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unsigned int s;
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};
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struct mgag200_crtc_state {
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struct drm_crtc_state base;
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/* Primary-plane format; required for modesetting and color mgmt. */
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const struct drm_format_info *format;
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struct mgag200_pll_values pixpllc;
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};
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static inline struct mgag200_crtc_state *to_mgag200_crtc_state(struct drm_crtc_state *base)
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{
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return container_of(base, struct mgag200_crtc_state, base);
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}
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struct mga_i2c_chan {
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struct i2c_adapter adapter;
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struct drm_device *dev;
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struct i2c_algo_bit_data bit;
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int data, clock;
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};
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enum mga_type {
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G200_PCI,
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G200_AGP,
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G200_SE_A,
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G200_SE_B,
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G200_WB,
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G200_EV,
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G200_EH,
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G200_EH3,
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G200_ER,
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G200_EW3,
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};
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struct mgag200_device_info {
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u16 max_hdisplay;
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u16 max_vdisplay;
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/*
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* Maximum memory bandwidth (MiB/sec). Setting this to zero disables
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* the rsp test during mode validation.
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*/
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unsigned long max_mem_bandwidth;
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/* HW has external source (e.g., BMC) to synchronize with */
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bool has_vidrst:1;
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struct {
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unsigned data_bit:3;
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unsigned clock_bit:3;
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} i2c;
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/*
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* HW does not handle 'startadd' register correctly. Always set
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* it's value to 0.
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*/
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bool bug_no_startadd:1;
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};
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#define MGAG200_DEVICE_INFO_INIT(_max_hdisplay, _max_vdisplay, _max_mem_bandwidth, \
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_has_vidrst, _i2c_data_bit, _i2c_clock_bit, \
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_bug_no_startadd) \
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{ \
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.max_hdisplay = (_max_hdisplay), \
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.max_vdisplay = (_max_vdisplay), \
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.max_mem_bandwidth = (_max_mem_bandwidth), \
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.has_vidrst = (_has_vidrst), \
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.i2c = { \
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.data_bit = (_i2c_data_bit), \
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.clock_bit = (_i2c_clock_bit), \
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}, \
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.bug_no_startadd = (_bug_no_startadd), \
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}
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struct mgag200_device_funcs {
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/*
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* Disables an external reset source (i.e., BMC) before programming
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* a new display mode.
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*/
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void (*disable_vidrst)(struct mga_device *mdev);
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/*
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* Enables an external reset source (i.e., BMC) after programming
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* a new display mode.
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*/
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void (*enable_vidrst)(struct mga_device *mdev);
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/*
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* Validate that the given state can be programmed into PIXPLLC. On
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* success, the calculated parameters should be stored in the CRTC's
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* state in struct @mgag200_crtc_state.pixpllc.
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*/
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int (*pixpllc_atomic_check)(struct drm_crtc *crtc, struct drm_atomic_state *new_state);
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/*
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* Program PIXPLLC from the CRTC state. The parameters should have been
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* stored in struct @mgag200_crtc_state.pixpllc by the corresponding
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* implementation of @pixpllc_atomic_check.
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*/
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void (*pixpllc_atomic_update)(struct drm_crtc *crtc, struct drm_atomic_state *old_state);
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};
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struct mga_device {
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struct drm_device base;
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const struct mgag200_device_info *info;
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const struct mgag200_device_funcs *funcs;
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struct resource *rmmio_res;
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void __iomem *rmmio;
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struct mutex rmmio_lock; /* Protects access to rmmio */
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struct resource *vram_res;
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void __iomem *vram;
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resource_size_t vram_available;
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struct drm_plane primary_plane;
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struct drm_crtc crtc;
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struct drm_encoder encoder;
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struct mga_i2c_chan i2c;
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struct drm_connector connector;
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};
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static inline struct mga_device *to_mga_device(struct drm_device *dev)
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{
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return container_of(dev, struct mga_device, base);
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}
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struct mgag200_g200_device {
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struct mga_device base;
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/* PLL constants */
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long ref_clk;
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long pclk_min;
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long pclk_max;
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};
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static inline struct mgag200_g200_device *to_mgag200_g200_device(struct drm_device *dev)
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{
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return container_of(to_mga_device(dev), struct mgag200_g200_device, base);
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}
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struct mgag200_g200se_device {
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struct mga_device base;
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/* SE model number stored in reg 0x1e24 */
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u32 unique_rev_id;
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};
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static inline struct mgag200_g200se_device *to_mgag200_g200se_device(struct drm_device *dev)
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{
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return container_of(to_mga_device(dev), struct mgag200_g200se_device, base);
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}
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/* mgag200_drv.c */
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int mgag200_init_pci_options(struct pci_dev *pdev, u32 option, u32 option2);
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resource_size_t mgag200_probe_vram(void __iomem *mem, resource_size_t size);
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resource_size_t mgag200_device_probe_vram(struct mga_device *mdev);
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int mgag200_device_preinit(struct mga_device *mdev);
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int mgag200_device_init(struct mga_device *mdev,
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const struct mgag200_device_info *info,
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const struct mgag200_device_funcs *funcs);
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/* mgag200_<device type>.c */
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struct mga_device *mgag200_g200_device_create(struct pci_dev *pdev, const struct drm_driver *drv);
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struct mga_device *mgag200_g200se_device_create(struct pci_dev *pdev, const struct drm_driver *drv,
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enum mga_type type);
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void mgag200_g200wb_init_registers(struct mga_device *mdev);
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void mgag200_g200wb_pixpllc_atomic_update(struct drm_crtc *crtc, struct drm_atomic_state *old_state);
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struct mga_device *mgag200_g200wb_device_create(struct pci_dev *pdev, const struct drm_driver *drv);
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struct mga_device *mgag200_g200ev_device_create(struct pci_dev *pdev, const struct drm_driver *drv);
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void mgag200_g200eh_init_registers(struct mga_device *mdev);
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void mgag200_g200eh_pixpllc_atomic_update(struct drm_crtc *crtc, struct drm_atomic_state *old_state);
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struct mga_device *mgag200_g200eh_device_create(struct pci_dev *pdev,
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const struct drm_driver *drv);
|
||
|
|
struct mga_device *mgag200_g200eh3_device_create(struct pci_dev *pdev,
|
||
|
|
const struct drm_driver *drv);
|
||
|
|
struct mga_device *mgag200_g200er_device_create(struct pci_dev *pdev,
|
||
|
|
const struct drm_driver *drv);
|
||
|
|
struct mga_device *mgag200_g200ew3_device_create(struct pci_dev *pdev,
|
||
|
|
const struct drm_driver *drv);
|
||
|
|
|
||
|
|
/*
|
||
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* mgag200_mode.c
|
||
|
|
*/
|
||
|
|
|
||
|
|
struct drm_crtc;
|
||
|
|
struct drm_crtc_state;
|
||
|
|
struct drm_display_mode;
|
||
|
|
struct drm_plane;
|
||
|
|
struct drm_atomic_state;
|
||
|
|
|
||
|
|
extern const uint32_t mgag200_primary_plane_formats[];
|
||
|
|
extern const size_t mgag200_primary_plane_formats_size;
|
||
|
|
extern const uint64_t mgag200_primary_plane_fmtmods[];
|
||
|
|
|
||
|
|
int mgag200_primary_plane_helper_atomic_check(struct drm_plane *plane,
|
||
|
|
struct drm_atomic_state *new_state);
|
||
|
|
void mgag200_primary_plane_helper_atomic_update(struct drm_plane *plane,
|
||
|
|
struct drm_atomic_state *old_state);
|
||
|
|
void mgag200_primary_plane_helper_atomic_disable(struct drm_plane *plane,
|
||
|
|
struct drm_atomic_state *old_state);
|
||
|
|
#define MGAG200_PRIMARY_PLANE_HELPER_FUNCS \
|
||
|
|
DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, \
|
||
|
|
.atomic_check = mgag200_primary_plane_helper_atomic_check, \
|
||
|
|
.atomic_update = mgag200_primary_plane_helper_atomic_update, \
|
||
|
|
.atomic_disable = mgag200_primary_plane_helper_atomic_disable
|
||
|
|
|
||
|
|
#define MGAG200_PRIMARY_PLANE_FUNCS \
|
||
|
|
.update_plane = drm_atomic_helper_update_plane, \
|
||
|
|
.disable_plane = drm_atomic_helper_disable_plane, \
|
||
|
|
.destroy = drm_plane_cleanup, \
|
||
|
|
DRM_GEM_SHADOW_PLANE_FUNCS
|
||
|
|
|
||
|
|
enum drm_mode_status mgag200_crtc_helper_mode_valid(struct drm_crtc *crtc,
|
||
|
|
const struct drm_display_mode *mode);
|
||
|
|
int mgag200_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *new_state);
|
||
|
|
void mgag200_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *old_state);
|
||
|
|
void mgag200_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *old_state);
|
||
|
|
void mgag200_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *old_state);
|
||
|
|
|
||
|
|
#define MGAG200_CRTC_HELPER_FUNCS \
|
||
|
|
.mode_valid = mgag200_crtc_helper_mode_valid, \
|
||
|
|
.atomic_check = mgag200_crtc_helper_atomic_check, \
|
||
|
|
.atomic_flush = mgag200_crtc_helper_atomic_flush, \
|
||
|
|
.atomic_enable = mgag200_crtc_helper_atomic_enable, \
|
||
|
|
.atomic_disable = mgag200_crtc_helper_atomic_disable
|
||
|
|
|
||
|
|
void mgag200_crtc_reset(struct drm_crtc *crtc);
|
||
|
|
struct drm_crtc_state *mgag200_crtc_atomic_duplicate_state(struct drm_crtc *crtc);
|
||
|
|
void mgag200_crtc_atomic_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state);
|
||
|
|
|
||
|
|
#define MGAG200_CRTC_FUNCS \
|
||
|
|
.reset = mgag200_crtc_reset, \
|
||
|
|
.destroy = drm_crtc_cleanup, \
|
||
|
|
.set_config = drm_atomic_helper_set_config, \
|
||
|
|
.page_flip = drm_atomic_helper_page_flip, \
|
||
|
|
.atomic_duplicate_state = mgag200_crtc_atomic_duplicate_state, \
|
||
|
|
.atomic_destroy_state = mgag200_crtc_atomic_destroy_state
|
||
|
|
|
||
|
|
#define MGAG200_DAC_ENCODER_FUNCS \
|
||
|
|
.destroy = drm_encoder_cleanup
|
||
|
|
|
||
|
|
int mgag200_vga_connector_helper_get_modes(struct drm_connector *connector);
|
||
|
|
|
||
|
|
#define MGAG200_VGA_CONNECTOR_HELPER_FUNCS \
|
||
|
|
.get_modes = mgag200_vga_connector_helper_get_modes
|
||
|
|
|
||
|
|
#define MGAG200_VGA_CONNECTOR_FUNCS \
|
||
|
|
.reset = drm_atomic_helper_connector_reset, \
|
||
|
|
.fill_modes = drm_helper_probe_single_connector_modes, \
|
||
|
|
.destroy = drm_connector_cleanup, \
|
||
|
|
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, \
|
||
|
|
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state
|
||
|
|
|
||
|
|
void mgag200_set_mode_regs(struct mga_device *mdev, const struct drm_display_mode *mode);
|
||
|
|
void mgag200_set_format_regs(struct mga_device *mdev, const struct drm_format_info *format);
|
||
|
|
void mgag200_enable_display(struct mga_device *mdev);
|
||
|
|
void mgag200_init_registers(struct mga_device *mdev);
|
||
|
|
int mgag200_mode_config_init(struct mga_device *mdev, resource_size_t vram_available);
|
||
|
|
|
||
|
|
/* mgag200_bmc.c */
|
||
|
|
void mgag200_bmc_disable_vidrst(struct mga_device *mdev);
|
||
|
|
void mgag200_bmc_enable_vidrst(struct mga_device *mdev);
|
||
|
|
|
||
|
|
/* mgag200_i2c.c */
|
||
|
|
int mgag200_i2c_init(struct mga_device *mdev, struct mga_i2c_chan *i2c);
|
||
|
|
|
||
|
|
#endif /* __MGAG200_DRV_H__ */
|