320 lines
8.2 KiB
C
320 lines
8.2 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_drv.h>
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#include <drm/drm_gem_atomic_helper.h>
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#include <drm/drm_probe_helper.h>
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#include "mgag200_drv.h"
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void mgag200_g200eh_init_registers(struct mga_device *mdev)
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{
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static const u8 dacvalue[] = {
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MGAG200_DAC_DEFAULT(0x00, 0xc9,
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MGA1064_MISC_CTL_VGA8 | MGA1064_MISC_CTL_DAC_RAM_CS,
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0x00, 0x00, 0x00)
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};
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size_t i;
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for (i = 0; i < ARRAY_SIZE(dacvalue); i++) {
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if ((i <= 0x17) ||
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(i == 0x1b) ||
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(i == 0x1c) ||
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((i >= 0x1f) && (i <= 0x29)) ||
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((i >= 0x30) && (i <= 0x37)) ||
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((i >= 0x44) && (i <= 0x4e)))
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continue;
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WREG_DAC(i, dacvalue[i]);
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}
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mgag200_init_registers(mdev);
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}
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/*
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* PIXPLLC
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*/
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static int mgag200_g200eh_pixpllc_atomic_check(struct drm_crtc *crtc,
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struct drm_atomic_state *new_state)
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{
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static const unsigned int vcomax = 800000;
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static const unsigned int vcomin = 400000;
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static const unsigned int pllreffreq = 33333;
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struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(new_state, crtc);
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struct mgag200_crtc_state *new_mgag200_crtc_state = to_mgag200_crtc_state(new_crtc_state);
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long clock = new_crtc_state->mode.clock;
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struct mgag200_pll_values *pixpllc = &new_mgag200_crtc_state->pixpllc;
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unsigned int delta, tmpdelta;
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unsigned int testp, testm, testn;
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unsigned int p, m, n, s;
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unsigned int computed;
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m = n = p = s = 0;
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delta = 0xffffffff;
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for (testp = 16; testp > 0; testp >>= 1) {
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if (clock * testp > vcomax)
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continue;
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if (clock * testp < vcomin)
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continue;
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for (testm = 1; testm < 33; testm++) {
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for (testn = 17; testn < 257; testn++) {
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computed = (pllreffreq * testn) / (testm * testp);
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if (computed > clock)
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tmpdelta = computed - clock;
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else
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tmpdelta = clock - computed;
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if (tmpdelta < delta) {
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delta = tmpdelta;
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n = testn;
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m = testm;
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p = testp;
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}
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}
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}
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}
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pixpllc->m = m;
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pixpllc->n = n;
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pixpllc->p = p;
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pixpllc->s = s;
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return 0;
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}
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void mgag200_g200eh_pixpllc_atomic_update(struct drm_crtc *crtc,
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struct drm_atomic_state *old_state)
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{
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struct drm_device *dev = crtc->dev;
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struct mga_device *mdev = to_mga_device(dev);
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struct drm_crtc_state *crtc_state = crtc->state;
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struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);
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struct mgag200_pll_values *pixpllc = &mgag200_crtc_state->pixpllc;
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unsigned int pixpllcm, pixpllcn, pixpllcp, pixpllcs;
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u8 xpixpllcm, xpixpllcn, xpixpllcp, tmp;
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int i, j, tmpcount, vcount;
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bool pll_locked = false;
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pixpllcm = pixpllc->m - 1;
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pixpllcn = pixpllc->n - 1;
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pixpllcp = pixpllc->p - 1;
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pixpllcs = pixpllc->s;
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xpixpllcm = ((pixpllcn & BIT(8)) >> 1) | pixpllcm;
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xpixpllcn = pixpllcn;
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xpixpllcp = (pixpllcs << 3) | pixpllcp;
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WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK);
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for (i = 0; i <= 32 && pll_locked == false; i++) {
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WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
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tmp = RREG8(DAC_DATA);
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tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
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WREG8(DAC_DATA, tmp);
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tmp = RREG8(MGAREG_MEM_MISC_READ);
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tmp |= 0x3 << 2;
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WREG8(MGAREG_MEM_MISC_WRITE, tmp);
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WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
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tmp = RREG8(DAC_DATA);
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tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
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WREG8(DAC_DATA, tmp);
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udelay(500);
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WREG_DAC(MGA1064_EH_PIX_PLLC_M, xpixpllcm);
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WREG_DAC(MGA1064_EH_PIX_PLLC_N, xpixpllcn);
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WREG_DAC(MGA1064_EH_PIX_PLLC_P, xpixpllcp);
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udelay(500);
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WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
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tmp = RREG8(DAC_DATA);
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tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
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tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
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WREG8(DAC_DATA, tmp);
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WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
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tmp = RREG8(DAC_DATA);
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tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
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tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
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WREG8(DAC_DATA, tmp);
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vcount = RREG8(MGAREG_VCOUNT);
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for (j = 0; j < 30 && pll_locked == false; j++) {
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tmpcount = RREG8(MGAREG_VCOUNT);
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if (tmpcount < vcount)
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vcount = 0;
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if ((tmpcount - vcount) > 2)
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pll_locked = true;
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else
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udelay(5);
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}
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}
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}
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/*
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* Mode-setting pipeline
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*/
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static const struct drm_plane_helper_funcs mgag200_g200eh_primary_plane_helper_funcs = {
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MGAG200_PRIMARY_PLANE_HELPER_FUNCS,
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};
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static const struct drm_plane_funcs mgag200_g200eh_primary_plane_funcs = {
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MGAG200_PRIMARY_PLANE_FUNCS,
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};
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static const struct drm_crtc_helper_funcs mgag200_g200eh_crtc_helper_funcs = {
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MGAG200_CRTC_HELPER_FUNCS,
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};
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static const struct drm_crtc_funcs mgag200_g200eh_crtc_funcs = {
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MGAG200_CRTC_FUNCS,
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};
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static const struct drm_encoder_funcs mgag200_g200eh_dac_encoder_funcs = {
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MGAG200_DAC_ENCODER_FUNCS,
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};
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static const struct drm_connector_helper_funcs mgag200_g200eh_vga_connector_helper_funcs = {
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MGAG200_VGA_CONNECTOR_HELPER_FUNCS,
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};
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static const struct drm_connector_funcs mgag200_g200eh_vga_connector_funcs = {
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MGAG200_VGA_CONNECTOR_FUNCS,
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};
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static int mgag200_g200eh_pipeline_init(struct mga_device *mdev)
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{
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struct drm_device *dev = &mdev->base;
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struct drm_plane *primary_plane = &mdev->primary_plane;
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struct drm_crtc *crtc = &mdev->crtc;
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struct drm_encoder *encoder = &mdev->encoder;
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struct mga_i2c_chan *i2c = &mdev->i2c;
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struct drm_connector *connector = &mdev->connector;
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int ret;
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ret = drm_universal_plane_init(dev, primary_plane, 0,
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&mgag200_g200eh_primary_plane_funcs,
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mgag200_primary_plane_formats,
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mgag200_primary_plane_formats_size,
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mgag200_primary_plane_fmtmods,
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DRM_PLANE_TYPE_PRIMARY, NULL);
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if (ret) {
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drm_err(dev, "drm_universal_plane_init() failed: %d\n", ret);
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return ret;
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}
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drm_plane_helper_add(primary_plane, &mgag200_g200eh_primary_plane_helper_funcs);
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drm_plane_enable_fb_damage_clips(primary_plane);
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ret = drm_crtc_init_with_planes(dev, crtc, primary_plane, NULL,
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&mgag200_g200eh_crtc_funcs, NULL);
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if (ret) {
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drm_err(dev, "drm_crtc_init_with_planes() failed: %d\n", ret);
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return ret;
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}
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drm_crtc_helper_add(crtc, &mgag200_g200eh_crtc_helper_funcs);
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/* FIXME: legacy gamma tables, but atomic gamma doesn't work without */
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drm_mode_crtc_set_gamma_size(crtc, MGAG200_LUT_SIZE);
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drm_crtc_enable_color_mgmt(crtc, 0, false, MGAG200_LUT_SIZE);
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encoder->possible_crtcs = drm_crtc_mask(crtc);
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ret = drm_encoder_init(dev, encoder, &mgag200_g200eh_dac_encoder_funcs,
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DRM_MODE_ENCODER_DAC, NULL);
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if (ret) {
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drm_err(dev, "drm_encoder_init() failed: %d\n", ret);
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return ret;
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}
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ret = mgag200_i2c_init(mdev, i2c);
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if (ret) {
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drm_err(dev, "failed to add DDC bus: %d\n", ret);
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return ret;
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}
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ret = drm_connector_init_with_ddc(dev, connector,
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&mgag200_g200eh_vga_connector_funcs,
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DRM_MODE_CONNECTOR_VGA,
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&i2c->adapter);
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if (ret) {
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drm_err(dev, "drm_connector_init_with_ddc() failed: %d\n", ret);
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return ret;
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}
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drm_connector_helper_add(connector, &mgag200_g200eh_vga_connector_helper_funcs);
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ret = drm_connector_attach_encoder(connector, encoder);
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if (ret) {
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drm_err(dev, "drm_connector_attach_encoder() failed: %d\n", ret);
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return ret;
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}
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return 0;
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}
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/*
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* DRM device
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*/
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static const struct mgag200_device_info mgag200_g200eh_device_info =
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MGAG200_DEVICE_INFO_INIT(2048, 2048, 37500, false, 1, 0, false);
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static const struct mgag200_device_funcs mgag200_g200eh_device_funcs = {
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.pixpllc_atomic_check = mgag200_g200eh_pixpllc_atomic_check,
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.pixpllc_atomic_update = mgag200_g200eh_pixpllc_atomic_update,
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};
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struct mga_device *mgag200_g200eh_device_create(struct pci_dev *pdev, const struct drm_driver *drv)
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{
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struct mga_device *mdev;
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struct drm_device *dev;
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resource_size_t vram_available;
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int ret;
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mdev = devm_drm_dev_alloc(&pdev->dev, drv, struct mga_device, base);
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if (IS_ERR(mdev))
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return mdev;
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dev = &mdev->base;
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pci_set_drvdata(pdev, dev);
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ret = mgag200_init_pci_options(pdev, 0x00000120, 0x0000b000);
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if (ret)
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return ERR_PTR(ret);
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ret = mgag200_device_preinit(mdev);
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if (ret)
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return ERR_PTR(ret);
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ret = mgag200_device_init(mdev, &mgag200_g200eh_device_info,
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&mgag200_g200eh_device_funcs);
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if (ret)
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return ERR_PTR(ret);
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mgag200_g200eh_init_registers(mdev);
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vram_available = mgag200_device_probe_vram(mdev);
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ret = mgag200_mode_config_init(mdev, vram_available);
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if (ret)
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return ERR_PTR(ret);
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ret = mgag200_g200eh_pipeline_init(mdev);
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if (ret)
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return ERR_PTR(ret);
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drm_mode_config_reset(dev);
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return mdev;
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}
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