275 lines
7.2 KiB
C
275 lines
7.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* (C) COPYRIGHT 2014-2018 ARM Limited. All rights reserved. */
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/* Copyright 2019 Linaro, Ltd., Rob Herring <robh@kernel.org> */
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#ifndef __PANFROST_ISSUES_H__
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#define __PANFROST_ISSUES_H__
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#include <linux/bitops.h>
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#include "panfrost_device.h"
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/*
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* This is not a complete list of issues, but only the ones the driver needs
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* to care about.
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*/
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enum panfrost_hw_issue {
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/* Need way to guarantee that all previously-translated memory accesses
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* are committed */
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HW_ISSUE_6367,
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/* On job complete with non-done the cache is not flushed */
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HW_ISSUE_6787,
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/* Write of PRFCNT_CONFIG_MODE_MANUAL to PRFCNT_CONFIG causes a
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* instrumentation dump if PRFCNT_TILER_EN is enabled */
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HW_ISSUE_8186,
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/* TIB: Reports faults from a vtile which has not yet been allocated */
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HW_ISSUE_8245,
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/* uTLB deadlock could occur when writing to an invalid page at the
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* same time as access to a valid page in the same uTLB cache line ( ==
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* 4 PTEs == 16K block of mapping) */
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HW_ISSUE_8316,
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/* HT: TERMINATE for RUN command ignored if previous LOAD_DESCRIPTOR is
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* still executing */
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HW_ISSUE_8394,
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/* CSE: Sends a TERMINATED response for a task that should not be
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* terminated */
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HW_ISSUE_8401,
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/* Repeatedly Soft-stopping a job chain consisting of (Vertex Shader,
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* Cache Flush, Tiler) jobs causes DATA_INVALID_FAULT on tiler job. */
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HW_ISSUE_8408,
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/* Disable the Pause Buffer in the LS pipe. */
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HW_ISSUE_8443,
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/* Change in RMUs in use causes problems related with the core's SDC */
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HW_ISSUE_8987,
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/* Compute endpoint has a 4-deep queue of tasks, meaning a soft stop
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* won't complete until all 4 tasks have completed */
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HW_ISSUE_9435,
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/* HT: Tiler returns TERMINATED for non-terminated command */
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HW_ISSUE_9510,
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/* Occasionally the GPU will issue multiple page faults for the same
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* address before the MMU page table has been read by the GPU */
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HW_ISSUE_9630,
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/* RA DCD load request to SDC returns invalid load ignore causing
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* colour buffer mismatch */
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HW_ISSUE_10327,
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/* MMU TLB invalidation hazards */
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HW_ISSUE_10649,
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/* Missing cache flush in multi core-group configuration */
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HW_ISSUE_10676,
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/* Chicken bit on T72X for a hardware workaround in compiler */
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HW_ISSUE_10797,
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/* Soft-stopping fragment jobs might fail with TILE_RANGE_FAULT */
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HW_ISSUE_10817,
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/* Intermittent missing interrupt on job completion */
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HW_ISSUE_10883,
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/* Soft-stopping fragment jobs might fail with TILE_RANGE_ERROR
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* (similar to issue 10817) and can use #10817 workaround */
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HW_ISSUE_10959,
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/* Soft-stopped fragment shader job can restart with out-of-bound
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* restart index */
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HW_ISSUE_10969,
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/* Race condition can cause tile list corruption */
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HW_ISSUE_11020,
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/* Write buffer can cause tile list corruption */
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HW_ISSUE_11024,
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/* Pause buffer can cause a fragment job hang */
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HW_ISSUE_11035,
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/* Dynamic Core Scaling not supported due to errata */
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HW_ISSUE_11056,
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/* Clear encoder state for a hard stopped fragment job which is AFBC
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* encoded by soft resetting the GPU. Only for T76X r0p0, r0p1 and
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* r0p1_50rel0 */
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HW_ISSUE_T76X_3542,
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/* Keep tiler module clock on to prevent GPU stall */
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HW_ISSUE_T76X_3953,
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/* Must ensure L2 is not transitioning when we reset. Workaround with a
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* busy wait until L2 completes transition; ensure there is a maximum
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* loop count as she may never complete her transition. (On chips
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* without this errata, it's totally okay if L2 transitions.) */
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HW_ISSUE_TMIX_8463,
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/* Don't set SC_LS_ATTR_CHECK_DISABLE/SC_LS_ALLOW_ATTR_TYPES */
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GPUCORE_1619,
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/* When a hard-stop follows close after a soft-stop, the completion
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* code for the terminated job may be incorrectly set to STOPPED */
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HW_ISSUE_TMIX_8438,
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/* "Protected mode" is buggy on Mali-G31 some Bifrost chips, so the
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* kernel must fiddle with L2 caches to prevent data leakage */
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HW_ISSUE_TGOX_R1_1234,
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/* Must set SC_VAR_ALGORITHM */
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HW_ISSUE_TTRX_2968_TTRX_3162,
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/* Bus fault from occlusion query write may cause future fragment jobs
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* to hang */
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HW_ISSUE_TTRX_3076,
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/* Must issue a dummy job before starting real work to prevent hangs */
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HW_ISSUE_TTRX_3485,
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HW_ISSUE_END
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};
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#define hw_issues_all (\
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BIT_ULL(HW_ISSUE_9435))
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#define hw_issues_t600 (\
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BIT_ULL(HW_ISSUE_6367) | \
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BIT_ULL(HW_ISSUE_6787) | \
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BIT_ULL(HW_ISSUE_8408) | \
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BIT_ULL(HW_ISSUE_9510) | \
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BIT_ULL(HW_ISSUE_10649) | \
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BIT_ULL(HW_ISSUE_10676) | \
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BIT_ULL(HW_ISSUE_10883) | \
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BIT_ULL(HW_ISSUE_11020) | \
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BIT_ULL(HW_ISSUE_11035) | \
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BIT_ULL(HW_ISSUE_11056) | \
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BIT_ULL(HW_ISSUE_TMIX_8438))
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#define hw_issues_t600_r0p0_15dev0 (\
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BIT_ULL(HW_ISSUE_8186) | \
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BIT_ULL(HW_ISSUE_8245) | \
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BIT_ULL(HW_ISSUE_8316) | \
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BIT_ULL(HW_ISSUE_8394) | \
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BIT_ULL(HW_ISSUE_8401) | \
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BIT_ULL(HW_ISSUE_8443) | \
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BIT_ULL(HW_ISSUE_8987) | \
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BIT_ULL(HW_ISSUE_9630) | \
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BIT_ULL(HW_ISSUE_10969) | \
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BIT_ULL(GPUCORE_1619))
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#define hw_issues_t620 (\
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BIT_ULL(HW_ISSUE_10649) | \
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BIT_ULL(HW_ISSUE_10883) | \
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BIT_ULL(HW_ISSUE_10959) | \
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BIT_ULL(HW_ISSUE_11056) | \
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BIT_ULL(HW_ISSUE_TMIX_8438))
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#define hw_issues_t620_r0p1 (\
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BIT_ULL(HW_ISSUE_10327) | \
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BIT_ULL(HW_ISSUE_10676) | \
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BIT_ULL(HW_ISSUE_10817) | \
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BIT_ULL(HW_ISSUE_11020) | \
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BIT_ULL(HW_ISSUE_11024) | \
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BIT_ULL(HW_ISSUE_11035))
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#define hw_issues_t620_r1p0 (\
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BIT_ULL(HW_ISSUE_11020) | \
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BIT_ULL(HW_ISSUE_11024))
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#define hw_issues_t720 (\
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BIT_ULL(HW_ISSUE_10649) | \
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BIT_ULL(HW_ISSUE_10797) | \
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BIT_ULL(HW_ISSUE_10883) | \
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BIT_ULL(HW_ISSUE_11056) | \
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BIT_ULL(HW_ISSUE_TMIX_8438))
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#define hw_issues_t760 (\
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BIT_ULL(HW_ISSUE_10883) | \
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BIT_ULL(HW_ISSUE_T76X_3953) | \
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BIT_ULL(HW_ISSUE_TMIX_8438))
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#define hw_issues_t760_r0p0 (\
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BIT_ULL(HW_ISSUE_11020) | \
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BIT_ULL(HW_ISSUE_11024) | \
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BIT_ULL(HW_ISSUE_T76X_3542))
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#define hw_issues_t760_r0p1 (\
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BIT_ULL(HW_ISSUE_11020) | \
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BIT_ULL(HW_ISSUE_11024) | \
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BIT_ULL(HW_ISSUE_T76X_3542))
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#define hw_issues_t760_r0p1_50rel0 (\
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BIT_ULL(HW_ISSUE_T76X_3542))
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#define hw_issues_t760_r0p2 (\
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BIT_ULL(HW_ISSUE_11020) | \
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BIT_ULL(HW_ISSUE_11024) | \
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BIT_ULL(HW_ISSUE_T76X_3542))
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#define hw_issues_t760_r0p3 (\
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BIT_ULL(HW_ISSUE_T76X_3542))
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#define hw_issues_t820 (\
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BIT_ULL(HW_ISSUE_10883) | \
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BIT_ULL(HW_ISSUE_T76X_3953) | \
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BIT_ULL(HW_ISSUE_TMIX_8438))
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#define hw_issues_t830 (\
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BIT_ULL(HW_ISSUE_10883) | \
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BIT_ULL(HW_ISSUE_T76X_3953) | \
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BIT_ULL(HW_ISSUE_TMIX_8438))
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#define hw_issues_t860 (\
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BIT_ULL(HW_ISSUE_10883) | \
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BIT_ULL(HW_ISSUE_T76X_3953) | \
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BIT_ULL(HW_ISSUE_TMIX_8438))
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#define hw_issues_t880 (\
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BIT_ULL(HW_ISSUE_10883) | \
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BIT_ULL(HW_ISSUE_T76X_3953) | \
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BIT_ULL(HW_ISSUE_TMIX_8438))
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#define hw_issues_g31 0
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#define hw_issues_g31_r1p0 (\
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BIT_ULL(HW_ISSUE_TGOX_R1_1234))
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#define hw_issues_g51 0
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#define hw_issues_g52 0
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#define hw_issues_g71 (\
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BIT_ULL(HW_ISSUE_TMIX_8463) | \
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BIT_ULL(HW_ISSUE_TMIX_8438))
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#define hw_issues_g71_r0p0_05dev0 (\
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BIT_ULL(HW_ISSUE_T76X_3953))
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#define hw_issues_g72 0
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#define hw_issues_g76 0
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#define hw_issues_g57 (\
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BIT_ULL(HW_ISSUE_TTRX_2968_TTRX_3162) | \
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BIT_ULL(HW_ISSUE_TTRX_3076))
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#define hw_issues_g57_r0p0 (\
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BIT_ULL(HW_ISSUE_TTRX_3485))
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static inline bool panfrost_has_hw_issue(const struct panfrost_device *pfdev,
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enum panfrost_hw_issue issue)
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{
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return test_bit(issue, pfdev->features.hw_issues);
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}
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#endif /* __PANFROST_ISSUES_H__ */
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