373 lines
20 KiB
C
373 lines
20 KiB
C
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/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#ifndef _SUMOD_H_
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#define _SUMOD_H_
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/* pm registers */
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/* rcu */
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#define RCU_FW_VERSION 0x30c
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#define RCU_PWR_GATING_SEQ0 0x408
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#define RCU_PWR_GATING_SEQ1 0x40c
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#define RCU_PWR_GATING_CNTL 0x410
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# define PWR_GATING_EN (1 << 0)
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# define RSVD_MASK (0x3 << 1)
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# define PCV(x) ((x) << 3)
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# define PCV_MASK (0x1f << 3)
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# define PCV_SHIFT 3
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# define PCP(x) ((x) << 8)
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# define PCP_MASK (0xf << 8)
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# define PCP_SHIFT 8
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# define RPW(x) ((x) << 16)
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# define RPW_MASK (0xf << 16)
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# define RPW_SHIFT 16
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# define ID(x) ((x) << 24)
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# define ID_MASK (0xf << 24)
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# define ID_SHIFT 24
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# define PGS(x) ((x) << 28)
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# define PGS_MASK (0xf << 28)
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# define PGS_SHIFT 28
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#define RCU_ALTVDDNB_NOTIFY 0x430
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#define RCU_LCLK_SCALING_CNTL 0x434
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# define LCLK_SCALING_EN (1 << 0)
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# define LCLK_SCALING_TYPE (1 << 1)
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# define LCLK_SCALING_TIMER_PRESCALER(x) ((x) << 4)
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# define LCLK_SCALING_TIMER_PRESCALER_MASK (0xf << 4)
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# define LCLK_SCALING_TIMER_PRESCALER_SHIFT 4
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# define LCLK_SCALING_TIMER_PERIOD(x) ((x) << 16)
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# define LCLK_SCALING_TIMER_PERIOD_MASK (0xf << 16)
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# define LCLK_SCALING_TIMER_PERIOD_SHIFT 16
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#define RCU_PWR_GATING_CNTL_2 0x4a0
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# define MPPU(x) ((x) << 0)
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# define MPPU_MASK (0xffff << 0)
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# define MPPU_SHIFT 0
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# define MPPD(x) ((x) << 16)
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# define MPPD_MASK (0xffff << 16)
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# define MPPD_SHIFT 16
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#define RCU_PWR_GATING_CNTL_3 0x4a4
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# define DPPU(x) ((x) << 0)
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# define DPPU_MASK (0xffff << 0)
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# define DPPU_SHIFT 0
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# define DPPD(x) ((x) << 16)
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# define DPPD_MASK (0xffff << 16)
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# define DPPD_SHIFT 16
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#define RCU_PWR_GATING_CNTL_4 0x4a8
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# define RT(x) ((x) << 0)
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# define RT_MASK (0xffff << 0)
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# define RT_SHIFT 0
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# define IT(x) ((x) << 16)
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# define IT_MASK (0xffff << 16)
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# define IT_SHIFT 16
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/* yes these two have the same address */
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#define RCU_PWR_GATING_CNTL_5 0x504
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#define RCU_GPU_BOOST_DISABLE 0x508
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#define MCU_M3ARB_INDEX 0x504
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#define MCU_M3ARB_PARAMS 0x508
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#define RCU_GNB_PWR_REP_TIMER_CNTL 0x50C
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#define RCU_SclkDpmTdpLimit01 0x514
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#define RCU_SclkDpmTdpLimit23 0x518
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#define RCU_SclkDpmTdpLimit47 0x51C
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#define RCU_SclkDpmTdpLimitPG 0x520
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#define GNB_TDP_LIMIT 0x540
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#define RCU_BOOST_MARGIN 0x544
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#define RCU_THROTTLE_MARGIN 0x548
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#define SMU_PCIE_PG_ARGS 0x58C
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#define SMU_PCIE_PG_ARGS_2 0x598
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#define SMU_PCIE_PG_ARGS_3 0x59C
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/* mmio */
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#define RCU_STATUS 0x11c
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# define GMC_PWR_GATER_BUSY (1 << 8)
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# define GFX_PWR_GATER_BUSY (1 << 9)
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# define UVD_PWR_GATER_BUSY (1 << 10)
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# define PCIE_PWR_GATER_BUSY (1 << 11)
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# define GMC_PWR_GATER_STATE (1 << 12)
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# define GFX_PWR_GATER_STATE (1 << 13)
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# define UVD_PWR_GATER_STATE (1 << 14)
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# define PCIE_PWR_GATER_STATE (1 << 15)
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# define GFX1_PWR_GATER_BUSY (1 << 16)
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# define GFX2_PWR_GATER_BUSY (1 << 17)
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# define GFX1_PWR_GATER_STATE (1 << 18)
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# define GFX2_PWR_GATER_STATE (1 << 19)
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#define GFX_INT_REQ 0x120
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# define INT_REQ (1 << 0)
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# define SERV_INDEX(x) ((x) << 1)
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# define SERV_INDEX_MASK (0xff << 1)
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# define SERV_INDEX_SHIFT 1
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#define GFX_INT_STATUS 0x124
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# define INT_ACK (1 << 0)
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# define INT_DONE (1 << 1)
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#define CG_SCLK_CNTL 0x600
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# define SCLK_DIVIDER(x) ((x) << 0)
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# define SCLK_DIVIDER_MASK (0x7f << 0)
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# define SCLK_DIVIDER_SHIFT 0
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#define CG_SCLK_STATUS 0x604
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# define SCLK_OVERCLK_DETECT (1 << 2)
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#define CG_DCLK_CNTL 0x610
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# define DCLK_DIVIDER_MASK 0x7f
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# define DCLK_DIR_CNTL_EN (1 << 8)
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#define CG_DCLK_STATUS 0x614
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# define DCLK_STATUS (1 << 0)
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#define CG_VCLK_CNTL 0x618
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# define VCLK_DIVIDER_MASK 0x7f
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# define VCLK_DIR_CNTL_EN (1 << 8)
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#define CG_VCLK_STATUS 0x61c
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#define GENERAL_PWRMGT 0x63c
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# define STATIC_PM_EN (1 << 1)
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#define SCLK_PWRMGT_CNTL 0x644
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# define SCLK_PWRMGT_OFF (1 << 0)
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# define SCLK_LOW_D1 (1 << 1)
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# define FIR_RESET (1 << 4)
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# define FIR_FORCE_TREND_SEL (1 << 5)
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# define FIR_TREND_MODE (1 << 6)
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# define DYN_GFX_CLK_OFF_EN (1 << 7)
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# define GFX_CLK_FORCE_ON (1 << 8)
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# define GFX_CLK_REQUEST_OFF (1 << 9)
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# define GFX_CLK_FORCE_OFF (1 << 10)
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# define GFX_CLK_OFF_ACPI_D1 (1 << 11)
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# define GFX_CLK_OFF_ACPI_D2 (1 << 12)
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# define GFX_CLK_OFF_ACPI_D3 (1 << 13)
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# define GFX_VOLTAGE_CHANGE_EN (1 << 16)
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# define GFX_VOLTAGE_CHANGE_MODE (1 << 17)
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#define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c
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# define TARG_SCLK_INDEX(x) ((x) << 6)
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# define TARG_SCLK_INDEX_MASK (0x7 << 6)
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# define TARG_SCLK_INDEX_SHIFT 6
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# define CURR_SCLK_INDEX(x) ((x) << 9)
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# define CURR_SCLK_INDEX_MASK (0x7 << 9)
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# define CURR_SCLK_INDEX_SHIFT 9
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# define TARG_INDEX(x) ((x) << 12)
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# define TARG_INDEX_MASK (0x7 << 12)
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# define TARG_INDEX_SHIFT 12
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# define CURR_INDEX(x) ((x) << 15)
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# define CURR_INDEX_MASK (0x7 << 15)
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# define CURR_INDEX_SHIFT 15
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#define CG_SCLK_DPM_CTRL 0x684
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# define SCLK_FSTATE_0_DIV(x) ((x) << 0)
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# define SCLK_FSTATE_0_DIV_MASK (0x7f << 0)
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# define SCLK_FSTATE_0_DIV_SHIFT 0
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# define SCLK_FSTATE_0_VLD (1 << 7)
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# define SCLK_FSTATE_1_DIV(x) ((x) << 8)
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# define SCLK_FSTATE_1_DIV_MASK (0x7f << 8)
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# define SCLK_FSTATE_1_DIV_SHIFT 8
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# define SCLK_FSTATE_1_VLD (1 << 15)
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# define SCLK_FSTATE_2_DIV(x) ((x) << 16)
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# define SCLK_FSTATE_2_DIV_MASK (0x7f << 16)
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# define SCLK_FSTATE_2_DIV_SHIFT 16
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# define SCLK_FSTATE_2_VLD (1 << 23)
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# define SCLK_FSTATE_3_DIV(x) ((x) << 24)
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# define SCLK_FSTATE_3_DIV_MASK (0x7f << 24)
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# define SCLK_FSTATE_3_DIV_SHIFT 24
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# define SCLK_FSTATE_3_VLD (1 << 31)
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#define CG_SCLK_DPM_CTRL_2 0x688
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#define CG_GCOOR 0x68c
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# define PHC(x) ((x) << 0)
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# define PHC_MASK (0x1f << 0)
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# define PHC_SHIFT 0
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# define SDC(x) ((x) << 9)
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# define SDC_MASK (0x3ff << 9)
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# define SDC_SHIFT 9
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# define SU(x) ((x) << 23)
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# define SU_MASK (0xf << 23)
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# define SU_SHIFT 23
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# define DIV_ID(x) ((x) << 28)
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# define DIV_ID_MASK (0x7 << 28)
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# define DIV_ID_SHIFT 28
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#define CG_FTV 0x690
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#define CG_FFCT_0 0x694
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# define UTC_0(x) ((x) << 0)
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# define UTC_0_MASK (0x3ff << 0)
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# define UTC_0_SHIFT 0
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# define DTC_0(x) ((x) << 10)
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# define DTC_0_MASK (0x3ff << 10)
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# define DTC_0_SHIFT 10
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#define CG_GIT 0x6d8
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# define CG_GICST(x) ((x) << 0)
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# define CG_GICST_MASK (0xffff << 0)
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# define CG_GICST_SHIFT 0
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# define CG_GIPOT(x) ((x) << 16)
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# define CG_GIPOT_MASK (0xffff << 16)
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# define CG_GIPOT_SHIFT 16
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#define CG_SCLK_DPM_CTRL_3 0x6e0
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# define FORCE_SCLK_STATE(x) ((x) << 0)
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# define FORCE_SCLK_STATE_MASK (0x7 << 0)
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# define FORCE_SCLK_STATE_SHIFT 0
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# define FORCE_SCLK_STATE_EN (1 << 3)
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# define GNB_TT(x) ((x) << 8)
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# define GNB_TT_MASK (0xff << 8)
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# define GNB_TT_SHIFT 8
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# define GNB_THERMTHRO_MASK (1 << 16)
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# define CNB_THERMTHRO_MASK_SCLK (1 << 17)
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# define DPM_SCLK_ENABLE (1 << 18)
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# define GNB_SLOW_FSTATE_0_MASK (1 << 23)
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# define GNB_SLOW_FSTATE_0_SHIFT 23
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# define FORCE_NB_PSTATE_1 (1 << 31)
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#define CG_SSP 0x6e8
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# define SST(x) ((x) << 0)
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# define SST_MASK (0xffff << 0)
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# define SST_SHIFT 0
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# define SSTU(x) ((x) << 16)
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# define SSTU_MASK (0xffff << 16)
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# define SSTU_SHIFT 16
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#define CG_ACPI_CNTL 0x70c
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# define SCLK_ACPI_DIV(x) ((x) << 0)
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# define SCLK_ACPI_DIV_MASK (0x7f << 0)
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# define SCLK_ACPI_DIV_SHIFT 0
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#define CG_SCLK_DPM_CTRL_4 0x71c
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# define DC_HDC(x) ((x) << 14)
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# define DC_HDC_MASK (0x3fff << 14)
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# define DC_HDC_SHIFT 14
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# define DC_HU(x) ((x) << 28)
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# define DC_HU_MASK (0xf << 28)
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# define DC_HU_SHIFT 28
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#define CG_SCLK_DPM_CTRL_5 0x720
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# define SCLK_FSTATE_BOOTUP(x) ((x) << 0)
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# define SCLK_FSTATE_BOOTUP_MASK (0x7 << 0)
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# define SCLK_FSTATE_BOOTUP_SHIFT 0
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# define TT_TP(x) ((x) << 3)
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# define TT_TP_MASK (0xffff << 3)
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# define TT_TP_SHIFT 3
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# define TT_TU(x) ((x) << 19)
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# define TT_TU_MASK (0xff << 19)
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# define TT_TU_SHIFT 19
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#define CG_SCLK_DPM_CTRL_6 0x724
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#define CG_AT_0 0x728
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# define CG_R(x) ((x) << 0)
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# define CG_R_MASK (0xffff << 0)
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# define CG_R_SHIFT 0
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# define CG_L(x) ((x) << 16)
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# define CG_L_MASK (0xffff << 16)
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# define CG_L_SHIFT 16
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#define CG_AT_1 0x72c
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#define CG_AT_2 0x730
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#define CG_THERMAL_INT 0x734
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#define DIG_THERM_INTH(x) ((x) << 8)
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#define DIG_THERM_INTH_MASK 0x0000FF00
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#define DIG_THERM_INTH_SHIFT 8
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#define DIG_THERM_INTL(x) ((x) << 16)
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#define DIG_THERM_INTL_MASK 0x00FF0000
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#define DIG_THERM_INTL_SHIFT 16
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#define THERM_INT_MASK_HIGH (1 << 24)
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#define THERM_INT_MASK_LOW (1 << 25)
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#define CG_AT_3 0x738
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#define CG_AT_4 0x73c
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#define CG_AT_5 0x740
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#define CG_AT_6 0x744
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#define CG_AT_7 0x748
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#define CG_BSP_0 0x750
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# define BSP(x) ((x) << 0)
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# define BSP_MASK (0xffff << 0)
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# define BSP_SHIFT 0
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# define BSU(x) ((x) << 16)
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# define BSU_MASK (0xf << 16)
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# define BSU_SHIFT 16
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#define CG_CG_VOLTAGE_CNTL 0x770
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# define REQ (1 << 0)
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# define LEVEL(x) ((x) << 1)
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# define LEVEL_MASK (0x3 << 1)
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# define LEVEL_SHIFT 1
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# define CG_VOLTAGE_EN (1 << 3)
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# define FORCE (1 << 4)
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# define PERIOD(x) ((x) << 8)
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# define PERIOD_MASK (0xffff << 8)
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# define PERIOD_SHIFT 8
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# define UNIT(x) ((x) << 24)
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# define UNIT_MASK (0xf << 24)
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# define UNIT_SHIFT 24
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#define CG_ACPI_VOLTAGE_CNTL 0x780
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# define ACPI_VOLTAGE_EN (1 << 8)
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#define CG_DPM_VOLTAGE_CNTL 0x788
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# define DPM_STATE0_LEVEL_MASK (0x3 << 0)
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# define DPM_STATE0_LEVEL_SHIFT 0
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||
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# define DPM_VOLTAGE_EN (1 << 16)
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||
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||
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#define CG_PWR_GATING_CNTL 0x7ac
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||
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# define DYN_PWR_DOWN_EN (1 << 0)
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||
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# define ACPI_PWR_DOWN_EN (1 << 1)
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||
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# define GFX_CLK_OFF_PWR_DOWN_EN (1 << 2)
|
||
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# define IOC_DISGPU_PWR_DOWN_EN (1 << 3)
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||
|
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# define FORCE_POWR_ON (1 << 4)
|
||
|
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# define PGP(x) ((x) << 8)
|
||
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# define PGP_MASK (0xffff << 8)
|
||
|
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# define PGP_SHIFT 8
|
||
|
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# define PGU(x) ((x) << 24)
|
||
|
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# define PGU_MASK (0xf << 24)
|
||
|
|
# define PGU_SHIFT 24
|
||
|
|
|
||
|
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#define CG_CGTT_LOCAL_0 0x7d0
|
||
|
|
#define CG_CGTT_LOCAL_1 0x7d4
|
||
|
|
|
||
|
|
#define DEEP_SLEEP_CNTL 0x818
|
||
|
|
# define R_DIS (1 << 3)
|
||
|
|
# define HS(x) ((x) << 4)
|
||
|
|
# define HS_MASK (0xfff << 4)
|
||
|
|
# define HS_SHIFT 4
|
||
|
|
# define ENABLE_DS (1 << 31)
|
||
|
|
#define DEEP_SLEEP_CNTL2 0x81c
|
||
|
|
# define LB_UFP_EN (1 << 0)
|
||
|
|
# define INOUT_C(x) ((x) << 4)
|
||
|
|
# define INOUT_C_MASK (0xff << 4)
|
||
|
|
# define INOUT_C_SHIFT 4
|
||
|
|
|
||
|
|
#define CG_SCRATCH2 0x824
|
||
|
|
|
||
|
|
#define CG_SCLK_DPM_CTRL_11 0x830
|
||
|
|
|
||
|
|
#define HW_REV 0x5564
|
||
|
|
# define ATI_REV_ID_MASK (0xf << 28)
|
||
|
|
# define ATI_REV_ID_SHIFT 28
|
||
|
|
/* 0 = A0, 1 = A1, 2 = B0, 3 = C0, etc. */
|
||
|
|
|
||
|
|
#define DOUT_SCRATCH3 0x611c
|
||
|
|
|
||
|
|
#define GB_ADDR_CONFIG 0x98f8
|
||
|
|
|
||
|
|
#endif
|