305 lines
9.2 KiB
C
305 lines
9.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
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/*
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* Copyright(c) 2015 - 2020 Intel Corporation.
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*/
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#ifndef _COMMON_H
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#define _COMMON_H
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#include <rdma/hfi/hfi1_user.h>
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/*
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* This file contains defines, structures, etc. that are used
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* to communicate between kernel and user code.
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*/
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/* version of protocol header (known to chip also). In the long run,
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* we should be able to generate and accept a range of version numbers;
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* for now we only accept one, and it's compiled in.
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*/
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#define IPS_PROTO_VERSION 2
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/*
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* These are compile time constants that you may want to enable or disable
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* if you are trying to debug problems with code or performance.
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* HFI1_VERBOSE_TRACING define as 1 if you want additional tracing in
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* fast path code
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* HFI1_TRACE_REGWRITES define as 1 if you want register writes to be
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* traced in fast path code
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* _HFI1_TRACING define as 0 if you want to remove all tracing in a
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* compilation unit
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*/
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/* driver/hw feature set bitmask */
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#define HFI1_CAP_USER_SHIFT 24
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#define HFI1_CAP_MASK ((1UL << HFI1_CAP_USER_SHIFT) - 1)
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/* locked flag - if set, only HFI1_CAP_WRITABLE_MASK bits can be set */
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#define HFI1_CAP_LOCKED_SHIFT 63
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#define HFI1_CAP_LOCKED_MASK 0x1ULL
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#define HFI1_CAP_LOCKED_SMASK (HFI1_CAP_LOCKED_MASK << HFI1_CAP_LOCKED_SHIFT)
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/* extra bits used between kernel and user processes */
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#define HFI1_CAP_MISC_SHIFT (HFI1_CAP_USER_SHIFT * 2)
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#define HFI1_CAP_MISC_MASK ((1ULL << (HFI1_CAP_LOCKED_SHIFT - \
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HFI1_CAP_MISC_SHIFT)) - 1)
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#define HFI1_CAP_KSET(cap) ({ hfi1_cap_mask |= HFI1_CAP_##cap; hfi1_cap_mask; })
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#define HFI1_CAP_KCLEAR(cap) \
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({ \
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hfi1_cap_mask &= ~HFI1_CAP_##cap; \
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hfi1_cap_mask; \
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})
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#define HFI1_CAP_USET(cap) \
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({ \
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hfi1_cap_mask |= (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
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hfi1_cap_mask; \
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})
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#define HFI1_CAP_UCLEAR(cap) \
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({ \
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hfi1_cap_mask &= ~(HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
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hfi1_cap_mask; \
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})
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#define HFI1_CAP_SET(cap) \
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({ \
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hfi1_cap_mask |= (HFI1_CAP_##cap | (HFI1_CAP_##cap << \
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HFI1_CAP_USER_SHIFT)); \
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hfi1_cap_mask; \
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})
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#define HFI1_CAP_CLEAR(cap) \
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({ \
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hfi1_cap_mask &= ~(HFI1_CAP_##cap | \
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(HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT)); \
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hfi1_cap_mask; \
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})
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#define HFI1_CAP_LOCK() \
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({ hfi1_cap_mask |= HFI1_CAP_LOCKED_SMASK; hfi1_cap_mask; })
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#define HFI1_CAP_LOCKED() (!!(hfi1_cap_mask & HFI1_CAP_LOCKED_SMASK))
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/*
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* The set of capability bits that can be changed after initial load
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* This set is the same for kernel and user contexts. However, for
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* user contexts, the set can be further filtered by using the
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* HFI1_CAP_RESERVED_MASK bits.
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*/
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#define HFI1_CAP_WRITABLE_MASK (HFI1_CAP_SDMA_AHG | \
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HFI1_CAP_HDRSUPP | \
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HFI1_CAP_MULTI_PKT_EGR | \
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HFI1_CAP_NODROP_RHQ_FULL | \
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HFI1_CAP_NODROP_EGR_FULL | \
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HFI1_CAP_ALLOW_PERM_JKEY | \
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HFI1_CAP_STATIC_RATE_CTRL | \
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HFI1_CAP_PRINT_UNIMPL | \
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HFI1_CAP_TID_UNMAP | \
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HFI1_CAP_OPFN)
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/*
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* A set of capability bits that are "global" and are not allowed to be
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* set in the user bitmask.
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*/
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#define HFI1_CAP_RESERVED_MASK ((HFI1_CAP_SDMA | \
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HFI1_CAP_USE_SDMA_HEAD | \
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HFI1_CAP_EXTENDED_PSN | \
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HFI1_CAP_PRINT_UNIMPL | \
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HFI1_CAP_NO_INTEGRITY | \
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HFI1_CAP_PKEY_CHECK | \
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HFI1_CAP_TID_RDMA | \
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HFI1_CAP_OPFN | \
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HFI1_CAP_AIP) << \
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HFI1_CAP_USER_SHIFT)
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/*
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* Set of capabilities that need to be enabled for kernel context in
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* order to be allowed for user contexts, as well.
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*/
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#define HFI1_CAP_MUST_HAVE_KERN (HFI1_CAP_STATIC_RATE_CTRL)
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/* Default enabled capabilities (both kernel and user) */
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#define HFI1_CAP_MASK_DEFAULT (HFI1_CAP_HDRSUPP | \
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HFI1_CAP_NODROP_RHQ_FULL | \
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HFI1_CAP_NODROP_EGR_FULL | \
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HFI1_CAP_SDMA | \
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HFI1_CAP_PRINT_UNIMPL | \
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HFI1_CAP_STATIC_RATE_CTRL | \
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HFI1_CAP_PKEY_CHECK | \
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HFI1_CAP_MULTI_PKT_EGR | \
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HFI1_CAP_EXTENDED_PSN | \
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HFI1_CAP_AIP | \
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((HFI1_CAP_HDRSUPP | \
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HFI1_CAP_MULTI_PKT_EGR | \
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HFI1_CAP_STATIC_RATE_CTRL | \
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HFI1_CAP_PKEY_CHECK | \
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HFI1_CAP_EARLY_CREDIT_RETURN) << \
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HFI1_CAP_USER_SHIFT))
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/*
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* A bitmask of kernel/global capabilities that should be communicated
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* to user level processes.
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*/
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#define HFI1_CAP_K2U (HFI1_CAP_SDMA | \
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HFI1_CAP_EXTENDED_PSN | \
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HFI1_CAP_PKEY_CHECK | \
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HFI1_CAP_NO_INTEGRITY)
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#define HFI1_USER_SWVERSION ((HFI1_USER_SWMAJOR << HFI1_SWMAJOR_SHIFT) | \
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HFI1_USER_SWMINOR)
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/*
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* The next set of defines are for packet headers, and chip register
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* and memory bits that are visible to and/or used by user-mode software.
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*/
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/*
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* Receive Header Flags
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*/
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#define RHF_PKT_LEN_SHIFT 0
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#define RHF_PKT_LEN_MASK 0xfffull
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#define RHF_PKT_LEN_SMASK (RHF_PKT_LEN_MASK << RHF_PKT_LEN_SHIFT)
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#define RHF_RCV_TYPE_SHIFT 12
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#define RHF_RCV_TYPE_MASK 0x7ull
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#define RHF_RCV_TYPE_SMASK (RHF_RCV_TYPE_MASK << RHF_RCV_TYPE_SHIFT)
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#define RHF_USE_EGR_BFR_SHIFT 15
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#define RHF_USE_EGR_BFR_MASK 0x1ull
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#define RHF_USE_EGR_BFR_SMASK (RHF_USE_EGR_BFR_MASK << RHF_USE_EGR_BFR_SHIFT)
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#define RHF_EGR_INDEX_SHIFT 16
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#define RHF_EGR_INDEX_MASK 0x7ffull
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#define RHF_EGR_INDEX_SMASK (RHF_EGR_INDEX_MASK << RHF_EGR_INDEX_SHIFT)
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#define RHF_DC_INFO_SHIFT 27
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#define RHF_DC_INFO_MASK 0x1ull
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#define RHF_DC_INFO_SMASK (RHF_DC_INFO_MASK << RHF_DC_INFO_SHIFT)
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#define RHF_RCV_SEQ_SHIFT 28
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#define RHF_RCV_SEQ_MASK 0xfull
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#define RHF_RCV_SEQ_SMASK (RHF_RCV_SEQ_MASK << RHF_RCV_SEQ_SHIFT)
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#define RHF_EGR_OFFSET_SHIFT 32
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#define RHF_EGR_OFFSET_MASK 0xfffull
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#define RHF_EGR_OFFSET_SMASK (RHF_EGR_OFFSET_MASK << RHF_EGR_OFFSET_SHIFT)
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#define RHF_HDRQ_OFFSET_SHIFT 44
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#define RHF_HDRQ_OFFSET_MASK 0x1ffull
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#define RHF_HDRQ_OFFSET_SMASK (RHF_HDRQ_OFFSET_MASK << RHF_HDRQ_OFFSET_SHIFT)
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#define RHF_K_HDR_LEN_ERR (0x1ull << 53)
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#define RHF_DC_UNC_ERR (0x1ull << 54)
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#define RHF_DC_ERR (0x1ull << 55)
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#define RHF_RCV_TYPE_ERR_SHIFT 56
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#define RHF_RCV_TYPE_ERR_MASK 0x7ul
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#define RHF_RCV_TYPE_ERR_SMASK (RHF_RCV_TYPE_ERR_MASK << RHF_RCV_TYPE_ERR_SHIFT)
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#define RHF_TID_ERR (0x1ull << 59)
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#define RHF_LEN_ERR (0x1ull << 60)
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#define RHF_ECC_ERR (0x1ull << 61)
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#define RHF_RESERVED (0x1ull << 62)
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#define RHF_ICRC_ERR (0x1ull << 63)
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#define RHF_ERROR_SMASK 0xffe0000000000000ull /* bits 63:53 */
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/* RHF receive types */
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#define RHF_RCV_TYPE_EXPECTED 0
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#define RHF_RCV_TYPE_EAGER 1
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#define RHF_RCV_TYPE_IB 2 /* normal IB, IB Raw, or IPv6 */
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#define RHF_RCV_TYPE_ERROR 3
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#define RHF_RCV_TYPE_BYPASS 4
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#define RHF_RCV_TYPE_INVALID5 5
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#define RHF_RCV_TYPE_INVALID6 6
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#define RHF_RCV_TYPE_INVALID7 7
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/* RHF receive type error - expected packet errors */
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#define RHF_RTE_EXPECTED_FLOW_SEQ_ERR 0x2
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#define RHF_RTE_EXPECTED_FLOW_GEN_ERR 0x4
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/* RHF receive type error - eager packet errors */
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#define RHF_RTE_EAGER_NO_ERR 0x0
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/* RHF receive type error - IB packet errors */
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#define RHF_RTE_IB_NO_ERR 0x0
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/* RHF receive type error - error packet errors */
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#define RHF_RTE_ERROR_NO_ERR 0x0
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#define RHF_RTE_ERROR_OP_CODE_ERR 0x1
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#define RHF_RTE_ERROR_KHDR_MIN_LEN_ERR 0x2
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#define RHF_RTE_ERROR_KHDR_HCRC_ERR 0x3
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#define RHF_RTE_ERROR_KHDR_KVER_ERR 0x4
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#define RHF_RTE_ERROR_CONTEXT_ERR 0x5
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#define RHF_RTE_ERROR_KHDR_TID_ERR 0x6
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/* RHF receive type error - bypass packet errors */
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#define RHF_RTE_BYPASS_NO_ERR 0x0
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/* MAX RcvSEQ */
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#define RHF_MAX_SEQ 13
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/* IB - LRH header constants */
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#define HFI1_LRH_GRH 0x0003 /* 1. word of IB LRH - next header: GRH */
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#define HFI1_LRH_BTH 0x0002 /* 1. word of IB LRH - next header: BTH */
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/* misc. */
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#define SC15_PACKET 0xF
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#define SIZE_OF_CRC 1
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#define SIZE_OF_LT 1
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#define MAX_16B_PADDING 12 /* CRC = 4, LT = 1, Pad = 0 to 7 bytes */
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#define LIM_MGMT_P_KEY 0x7FFF
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#define FULL_MGMT_P_KEY 0xFFFF
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#define DEFAULT_P_KEY LIM_MGMT_P_KEY
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#define HFI1_PSM_IOC_BASE_SEQ 0x0
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/* Number of BTH.PSN bits used for sequence number in expected rcvs */
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#define HFI1_KDETH_BTH_SEQ_SHIFT 11
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#define HFI1_KDETH_BTH_SEQ_MASK (BIT(HFI1_KDETH_BTH_SEQ_SHIFT) - 1)
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static inline __u64 rhf_to_cpu(const __le32 *rbuf)
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{
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return __le64_to_cpu(*((__le64 *)rbuf));
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}
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static inline u64 rhf_err_flags(u64 rhf)
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{
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return rhf & RHF_ERROR_SMASK;
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}
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static inline u32 rhf_rcv_type(u64 rhf)
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{
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return (rhf >> RHF_RCV_TYPE_SHIFT) & RHF_RCV_TYPE_MASK;
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}
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static inline u32 rhf_rcv_type_err(u64 rhf)
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{
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return (rhf >> RHF_RCV_TYPE_ERR_SHIFT) & RHF_RCV_TYPE_ERR_MASK;
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}
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/* return size is in bytes, not DWORDs */
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static inline u32 rhf_pkt_len(u64 rhf)
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{
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return ((rhf & RHF_PKT_LEN_SMASK) >> RHF_PKT_LEN_SHIFT) << 2;
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}
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static inline u32 rhf_egr_index(u64 rhf)
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{
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return (rhf >> RHF_EGR_INDEX_SHIFT) & RHF_EGR_INDEX_MASK;
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}
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static inline u32 rhf_rcv_seq(u64 rhf)
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{
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return (rhf >> RHF_RCV_SEQ_SHIFT) & RHF_RCV_SEQ_MASK;
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}
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/* returned offset is in DWORDS */
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static inline u32 rhf_hdrq_offset(u64 rhf)
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{
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return (rhf >> RHF_HDRQ_OFFSET_SHIFT) & RHF_HDRQ_OFFSET_MASK;
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}
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static inline u64 rhf_use_egr_bfr(u64 rhf)
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{
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return rhf & RHF_USE_EGR_BFR_SMASK;
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}
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static inline u64 rhf_dc_info(u64 rhf)
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{
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return rhf & RHF_DC_INFO_SMASK;
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}
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static inline u32 rhf_egr_buf_offset(u64 rhf)
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{
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return (rhf >> RHF_EGR_OFFSET_SHIFT) & RHF_EGR_OFFSET_MASK;
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}
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#endif /* _COMMON_H */
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