363 lines
9.8 KiB
C
363 lines
9.8 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Microchip Image Sensor Controller (ISC) driver header file
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*
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* Copyright (C) 2016-2019 Microchip Technology, Inc.
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*
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* Author: Songjun Wu
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* Author: Eugen Hristev <eugen.hristev@microchip.com>
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*
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*/
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#ifndef _ATMEL_ISC_H_
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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#include <media/videobuf2-dma-contig.h>
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#define ISC_CLK_MAX_DIV 255
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enum isc_clk_id {
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ISC_ISPCK = 0,
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ISC_MCK = 1,
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};
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struct isc_clk {
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struct clk_hw hw;
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struct clk *clk;
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struct regmap *regmap;
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spinlock_t lock; /* serialize access to clock registers */
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u8 id;
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u8 parent_id;
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u32 div;
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struct device *dev;
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};
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#define to_isc_clk(v) container_of(v, struct isc_clk, hw)
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struct isc_buffer {
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struct vb2_v4l2_buffer vb;
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struct list_head list;
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};
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struct isc_subdev_entity {
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struct v4l2_subdev *sd;
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struct v4l2_async_subdev *asd;
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struct device_node *epn;
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struct v4l2_async_notifier notifier;
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u32 pfe_cfg0;
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struct list_head list;
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};
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/*
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* struct isc_format - ISC media bus format information
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This structure represents the interface between the ISC
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and the sensor. It's the input format received by
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the ISC.
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* @fourcc: Fourcc code for this format
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* @mbus_code: V4L2 media bus format code.
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* @cfa_baycfg: If this format is RAW BAYER, indicate the type of bayer.
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this is either BGBG, RGRG, etc.
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* @pfe_cfg0_bps: Number of hardware data lines connected to the ISC
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*/
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struct isc_format {
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u32 fourcc;
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u32 mbus_code;
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u32 cfa_baycfg;
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bool sd_support;
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u32 pfe_cfg0_bps;
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};
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/* Pipeline bitmap */
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#define DPC_DPCENABLE BIT(0)
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#define DPC_GDCENABLE BIT(1)
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#define DPC_BLCENABLE BIT(2)
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#define WB_ENABLE BIT(3)
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#define CFA_ENABLE BIT(4)
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#define CC_ENABLE BIT(5)
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#define GAM_ENABLE BIT(6)
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#define GAM_BENABLE BIT(7)
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#define GAM_GENABLE BIT(8)
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#define GAM_RENABLE BIT(9)
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#define VHXS_ENABLE BIT(10)
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#define CSC_ENABLE BIT(11)
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#define CBC_ENABLE BIT(12)
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#define SUB422_ENABLE BIT(13)
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#define SUB420_ENABLE BIT(14)
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#define GAM_ENABLES (GAM_RENABLE | GAM_GENABLE | GAM_BENABLE | GAM_ENABLE)
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/*
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* struct fmt_config - ISC format configuration and internal pipeline
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This structure represents the internal configuration
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of the ISC.
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It also holds the format that ISC will present to v4l2.
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* @sd_format: Pointer to an isc_format struct that holds the sensor
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configuration.
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* @fourcc: Fourcc code for this format.
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* @bpp: Bytes per pixel in the current format.
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* @bpp_v4l2: Bytes per pixel in the current format, for v4l2.
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This differs from 'bpp' in the sense that in planar
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formats, it refers only to the first plane.
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* @rlp_cfg_mode: Configuration of the RLP (rounding, limiting packaging)
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* @dcfg_imode: Configuration of the input of the DMA module
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* @dctrl_dview: Configuration of the output of the DMA module
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* @bits_pipeline: Configuration of the pipeline, which modules are enabled
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*/
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struct fmt_config {
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struct isc_format *sd_format;
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u32 fourcc;
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u8 bpp;
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u8 bpp_v4l2;
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u32 rlp_cfg_mode;
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u32 dcfg_imode;
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u32 dctrl_dview;
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u32 bits_pipeline;
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};
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#define HIST_ENTRIES 512
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#define HIST_BAYER (ISC_HIS_CFG_MODE_B + 1)
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enum{
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HIST_INIT = 0,
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HIST_ENABLED,
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HIST_DISABLED,
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};
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struct isc_ctrls {
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struct v4l2_ctrl_handler handler;
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u32 brightness;
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u32 contrast;
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u8 gamma_index;
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#define ISC_WB_NONE 0
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#define ISC_WB_AUTO 1
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#define ISC_WB_ONETIME 2
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u8 awb;
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/* one for each component : GR, R, GB, B */
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u32 gain[HIST_BAYER];
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s32 offset[HIST_BAYER];
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u32 hist_entry[HIST_ENTRIES];
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u32 hist_count[HIST_BAYER];
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u8 hist_id;
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u8 hist_stat;
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#define HIST_MIN_INDEX 0
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#define HIST_MAX_INDEX 1
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u32 hist_minmax[HIST_BAYER][2];
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};
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#define ISC_PIPE_LINE_NODE_NUM 15
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/*
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* struct isc_reg_offsets - ISC device register offsets
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* @csc: Offset for the CSC register
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* @cbc: Offset for the CBC register
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* @sub422: Offset for the SUB422 register
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* @sub420: Offset for the SUB420 register
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* @rlp: Offset for the RLP register
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* @his: Offset for the HIS related registers
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* @dma: Offset for the DMA related registers
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* @version: Offset for the version register
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* @his_entry: Offset for the HIS entries registers
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*/
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struct isc_reg_offsets {
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u32 csc;
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u32 cbc;
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u32 sub422;
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u32 sub420;
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u32 rlp;
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u32 his;
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u32 dma;
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u32 version;
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u32 his_entry;
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};
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/*
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* struct isc_device - ISC device driver data/config struct
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* @regmap: Register map
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* @hclock: Hclock clock input (refer datasheet)
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* @ispck: iscpck clock (refer datasheet)
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* @isc_clks: ISC clocks
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* @ispck_required: ISC requires ISP Clock initialization
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* @dcfg: DMA master configuration, architecture dependent
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*
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* @dev: Registered device driver
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* @v4l2_dev: v4l2 registered device
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* @video_dev: registered video device
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*
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* @vb2_vidq: video buffer 2 video queue
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* @dma_queue_lock: lock to serialize the dma buffer queue
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* @dma_queue: the queue for dma buffers
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* @cur_frm: current isc frame/buffer
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* @sequence: current frame number
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* @stop: true if isc is not streaming, false if streaming
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* @comp: completion reference that signals frame completion
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*
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* @fmt: current v42l format
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* @user_formats: list of formats that are supported and agreed with sd
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* @num_user_formats: how many formats are in user_formats
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*
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* @config: current ISC format configuration
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* @try_config: the current ISC try format , not yet activated
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*
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* @ctrls: holds information about ISC controls
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* @do_wb_ctrl: control regarding the DO_WHITE_BALANCE button
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* @awb_work: workqueue reference for autowhitebalance histogram
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* analysis
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*
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* @lock: lock for serializing userspace file operations
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* with ISC operations
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* @awb_mutex: serialize access to streaming status from awb work queue
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* @awb_lock: lock for serializing awb work queue operations
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* with DMA/buffer operations
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*
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* @pipeline: configuration of the ISC pipeline
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*
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* @current_subdev: current subdevice: the sensor
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* @subdev_entities: list of subdevice entitites
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*
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* @gamma_table: pointer to the table with gamma values, has
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* gamma_max sets of GAMMA_ENTRIES entries each
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* @gamma_max: maximum number of sets of inside the gamma_table
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*
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* @max_width: maximum frame width, dependent on the internal RAM
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* @max_height: maximum frame height, dependent on the internal RAM
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*
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* @config_dpc: pointer to a function that initializes product
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* specific DPC module
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* @config_csc: pointer to a function that initializes product
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* specific CSC module
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* @config_cbc: pointer to a function that initializes product
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* specific CBC module
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* @config_cc: pointer to a function that initializes product
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* specific CC module
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* @config_gam: pointer to a function that initializes product
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* specific GAMMA module
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* @config_rlp: pointer to a function that initializes product
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* specific RLP module
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* @config_ctrls: pointer to a functoin that initializes product
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* specific v4l2 controls.
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*
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* @adapt_pipeline: pointer to a function that adapts the pipeline bits
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* to the product specific pipeline
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*
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* @offsets: struct holding the product specific register offsets
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* @controller_formats: pointer to the array of possible formats that the
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* controller can output
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* @formats_list: pointer to the array of possible formats that can
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* be used as an input to the controller
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* @controller_formats_size: size of controller_formats array
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* @formats_list_size: size of formats_list array
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*/
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struct isc_device {
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struct regmap *regmap;
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struct clk *hclock;
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struct clk *ispck;
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struct isc_clk isc_clks[2];
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bool ispck_required;
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u32 dcfg;
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struct device *dev;
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struct v4l2_device v4l2_dev;
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struct video_device video_dev;
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struct vb2_queue vb2_vidq;
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spinlock_t dma_queue_lock;
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struct list_head dma_queue;
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struct isc_buffer *cur_frm;
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unsigned int sequence;
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bool stop;
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struct completion comp;
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struct v4l2_format fmt;
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struct isc_format **user_formats;
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unsigned int num_user_formats;
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struct fmt_config config;
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struct fmt_config try_config;
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struct isc_ctrls ctrls;
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struct work_struct awb_work;
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struct mutex lock;
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struct mutex awb_mutex;
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spinlock_t awb_lock;
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struct regmap_field *pipeline[ISC_PIPE_LINE_NODE_NUM];
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struct isc_subdev_entity *current_subdev;
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struct list_head subdev_entities;
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struct {
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#define ISC_CTRL_DO_WB 1
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#define ISC_CTRL_R_GAIN 2
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#define ISC_CTRL_B_GAIN 3
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#define ISC_CTRL_GR_GAIN 4
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#define ISC_CTRL_GB_GAIN 5
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#define ISC_CTRL_R_OFF 6
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#define ISC_CTRL_B_OFF 7
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#define ISC_CTRL_GR_OFF 8
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#define ISC_CTRL_GB_OFF 9
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struct v4l2_ctrl *awb_ctrl;
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struct v4l2_ctrl *do_wb_ctrl;
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struct v4l2_ctrl *r_gain_ctrl;
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struct v4l2_ctrl *b_gain_ctrl;
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struct v4l2_ctrl *gr_gain_ctrl;
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struct v4l2_ctrl *gb_gain_ctrl;
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struct v4l2_ctrl *r_off_ctrl;
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struct v4l2_ctrl *b_off_ctrl;
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struct v4l2_ctrl *gr_off_ctrl;
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struct v4l2_ctrl *gb_off_ctrl;
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};
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#define GAMMA_ENTRIES 64
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/* pointer to the defined gamma table */
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const u32 (*gamma_table)[GAMMA_ENTRIES];
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u32 gamma_max;
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u32 max_width;
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u32 max_height;
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struct {
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void (*config_dpc)(struct isc_device *isc);
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void (*config_csc)(struct isc_device *isc);
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void (*config_cbc)(struct isc_device *isc);
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void (*config_cc)(struct isc_device *isc);
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void (*config_gam)(struct isc_device *isc);
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void (*config_rlp)(struct isc_device *isc);
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void (*config_ctrls)(struct isc_device *isc,
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const struct v4l2_ctrl_ops *ops);
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void (*adapt_pipeline)(struct isc_device *isc);
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};
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struct isc_reg_offsets offsets;
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const struct isc_format *controller_formats;
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struct isc_format *formats_list;
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u32 controller_formats_size;
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u32 formats_list_size;
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};
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extern const struct regmap_config isc_regmap_config;
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extern const struct v4l2_async_notifier_operations isc_async_ops;
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irqreturn_t isc_interrupt(int irq, void *dev_id);
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int isc_pipeline_init(struct isc_device *isc);
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int isc_clk_init(struct isc_device *isc);
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void isc_subdev_cleanup(struct isc_device *isc);
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void isc_clk_cleanup(struct isc_device *isc);
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#endif
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