137 lines
3.8 KiB
C
137 lines
3.8 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* NXP TDA18250BHN silicon tuner driver
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*
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* Copyright (C) 2017 Olli Salonen <olli.salonen@iki.fi>
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*/
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#ifndef TDA18250_PRIV_H
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#define TDA18250_PRIV_H
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#include "tda18250.h"
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#define R00_ID1 0x00 /* ID byte 1 */
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#define R01_ID2 0x01 /* ID byte 2 */
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#define R02_ID3 0x02 /* ID byte 3 */
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#define R03_THERMO1 0x03 /* Thermo byte 1 */
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#define R04_THERMO2 0x04 /* Thermo byte 2 */
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#define R05_POWER1 0x05 /* Power byte 1 */
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#define R06_POWER2 0x06 /* Power byte 2 */
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#define R07_GPIO 0x07 /* GPIO */
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#define R08_IRQ1 0x08 /* IRQ */
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#define R09_IRQ2 0x09 /* IRQ */
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#define R0A_IRQ3 0x0a /* IRQ */
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#define R0B_IRQ4 0x0b /* IRQ */
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#define R0C_AGC11 0x0c /* AGC1 byte 1 */
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#define R0D_AGC12 0x0d /* AGC1 byte 2 */
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#define R0E_AGC13 0x0e /* AGC1 byte 3 */
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#define R0F_AGC14 0x0f /* AGC1 byte 4 */
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#define R10_LT1 0x10 /* LT byte 1 */
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#define R11_LT2 0x11 /* LT byte 2 */
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#define R12_AGC21 0x12 /* AGC2 byte 1 */
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#define R13_AGC22 0x13 /* AGC2 byte 2 */
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#define R14_AGC23 0x14 /* AGC2 byte 3 */
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#define R15_AGC24 0x15 /* AGC2 byte 4 */
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#define R16_AGC25 0x16 /* AGC2 byte 5 */
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#define R17_AGC31 0x17 /* AGC3 byte 1 */
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#define R18_AGC32 0x18 /* AGC3 byte 2 */
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#define R19_AGC33 0x19 /* AGC3 byte 3 */
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#define R1A_AGCK 0x1a
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#define R1B_GAIN1 0x1b
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#define R1C_GAIN2 0x1c
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#define R1D_GAIN3 0x1d
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#define R1E_WI_FI 0x1e /* Wireless Filter */
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#define R1F_RF_BPF 0x1f /* RF Band Pass Filter */
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#define R20_IR_MIX 0x20 /* IR Mixer */
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#define R21_IF_AGC 0x21
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#define R22_IF1 0x22 /* IF byte 1 */
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#define R23_IF2 0x23 /* IF byte 2 */
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#define R24_IF3 0x24 /* IF byte 3 */
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#define R25_REF 0x25 /* reference byte */
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#define R26_IF 0x26 /* IF frequency */
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#define R27_RF1 0x27 /* RF frequency byte 1 */
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#define R28_RF2 0x28 /* RF frequency byte 2 */
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#define R29_RF3 0x29 /* RF frequency byte 3 */
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#define R2A_MSM1 0x2a
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#define R2B_MSM2 0x2b
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#define R2C_PS1 0x2c /* power saving mode byte 1 */
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#define R2D_PS2 0x2d /* power saving mode byte 2 */
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#define R2E_PS3 0x2e /* power saving mode byte 3 */
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#define R2F_RSSI1 0x2f
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#define R30_RSSI2 0x30
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#define R31_IRQ_CTRL 0x31
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#define R32_DUMMY 0x32
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#define R33_TEST 0x33
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#define R34_MD1 0x34
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#define R35_SD1 0x35
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#define R36_SD2 0x36
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#define R37_SD3 0x37
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#define R38_SD4 0x38
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#define R39_SD5 0x39
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#define R3A_SD_TEST 0x3a
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#define R3B_REGU 0x3b
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#define R3C_RCCAL1 0x3c
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#define R3D_RCCAL2 0x3d
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#define R3E_IRCAL1 0x3e
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#define R3F_IRCAL2 0x3f
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#define R40_IRCAL3 0x40
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#define R41_IRCAL4 0x41
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#define R42_IRCAL5 0x42
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#define R43_PD1 0x43 /* power down byte 1 */
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#define R44_PD2 0x44 /* power down byte 2 */
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#define R45_PD 0x45 /* power down */
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#define R46_CPUMP 0x46 /* charge pump */
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#define R47_LNAPOL 0x47 /* LNA polar casc */
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#define R48_SMOOTH1 0x48 /* smooth test byte 1 */
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#define R49_SMOOTH2 0x49 /* smooth test byte 2 */
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#define R4A_SMOOTH3 0x4a /* smooth test byte 3 */
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#define R4B_XTALOSC1 0x4b
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#define R4C_XTALOSC2 0x4c
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#define R4D_XTALFLX1 0x4d
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#define R4E_XTALFLX2 0x4e
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#define R4F_XTALFLX3 0x4f
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#define R50_XTALFLX4 0x50
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#define R51_XTALFLX5 0x51
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#define R52_IRLOOP0 0x52
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#define R53_IRLOOP1 0x53
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#define R54_IRLOOP2 0x54
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#define R55_IRLOOP3 0x55
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#define R56_IRLOOP4 0x56
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#define R57_PLL_LOG 0x57
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#define R58_AGC2_UP1 0x58
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#define R59_AGC2_UP2 0x59
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#define R5A_H3H5 0x5a
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#define R5B_AGC_AUTO 0x5b
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#define R5C_AGC_DEBUG 0x5c
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#define TDA18250_NUM_REGS 93
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#define TDA18250_POWER_STANDBY 0
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#define TDA18250_POWER_NORMAL 1
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#define TDA18250_IRQ_CAL 0x81
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#define TDA18250_IRQ_HW_INIT 0x82
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#define TDA18250_IRQ_TUNE 0x88
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struct tda18250_dev {
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struct mutex i2c_mutex;
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struct dvb_frontend *fe;
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struct i2c_adapter *i2c;
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struct regmap *regmap;
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u8 xtal_freq;
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/* IF in kHz */
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u16 if_dvbt_6;
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u16 if_dvbt_7;
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u16 if_dvbt_8;
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u16 if_dvbc_6;
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u16 if_dvbc_8;
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u16 if_atsc;
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u16 if_frequency;
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bool slave;
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bool loopthrough;
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bool warm;
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u8 regs[TDA18250_NUM_REGS];
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};
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#endif
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