51 lines
1.8 KiB
C
51 lines
1.8 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef TEGRA210_MC_H
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#define TEGRA210_MC_H
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#include "mc.h"
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/* register definitions */
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#define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4
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#define MC_LATENCY_ALLOWANCE_HC_0 0x310
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#define MC_LATENCY_ALLOWANCE_HC_1 0x314
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#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320
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#define MC_LATENCY_ALLOWANCE_NVENC_0 0x328
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#define MC_LATENCY_ALLOWANCE_PPCS_0 0x344
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#define MC_LATENCY_ALLOWANCE_PPCS_1 0x348
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#define MC_LATENCY_ALLOWANCE_ISP2_0 0x370
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#define MC_LATENCY_ALLOWANCE_ISP2_1 0x374
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#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c
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#define MC_LATENCY_ALLOWANCE_XUSB_1 0x380
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#define MC_LATENCY_ALLOWANCE_TSEC_0 0x390
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#define MC_LATENCY_ALLOWANCE_VIC_0 0x394
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#define MC_LATENCY_ALLOWANCE_VI2_0 0x398
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#define MC_LATENCY_ALLOWANCE_GPU_0 0x3ac
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#define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3b8
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#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 0x3bc
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#define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3c0
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#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3c4
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#define MC_LATENCY_ALLOWANCE_GPU2_0 0x3e8
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#define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3d8
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#define MC_MLL_MPCORER_PTSA_RATE 0x44c
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#define MC_FTOP_PTSA_RATE 0x50c
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#define MC_EMEM_ARB_TIMING_RFCPB 0x6c0
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#define MC_EMEM_ARB_TIMING_CCDMW 0x6c4
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#define MC_EMEM_ARB_REFPB_HP_CTRL 0x6f0
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#define MC_EMEM_ARB_REFPB_BANK_CTRL 0x6f4
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#define MC_PTSA_GRANT_DECREMENT 0x960
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#define MC_EMEM_ARB_DHYST_CTRL 0xbcc
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 0xbd0
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 0xbd4
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 0xbd8
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 0xbdc
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 0xbe0
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 0xbe4
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xbe8
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#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xbec
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#endif
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