358 lines
9.6 KiB
C
358 lines
9.6 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Marvell Octeon EP (EndPoint) Ethernet Driver
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*
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* Copyright (C) 2020 Marvell.
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*
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*/
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#ifndef _OCTEP_MAIN_H_
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#define _OCTEP_MAIN_H_
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#include "octep_tx.h"
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#include "octep_rx.h"
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#include "octep_ctrl_mbox.h"
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#define OCTEP_DRV_NAME "octeon_ep"
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#define OCTEP_DRV_STRING "Marvell Octeon EndPoint NIC Driver"
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#define OCTEP_PCIID_CN93_PF 0xB200177d
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#define OCTEP_PCIID_CN93_VF 0xB203177d
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#define OCTEP_PCI_DEVICE_ID_CN93_PF 0xB200
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#define OCTEP_PCI_DEVICE_ID_CN93_VF 0xB203
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#define OCTEP_MAX_QUEUES 63
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#define OCTEP_MAX_IQ OCTEP_MAX_QUEUES
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#define OCTEP_MAX_OQ OCTEP_MAX_QUEUES
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#define OCTEP_MAX_VF 64
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#define OCTEP_MAX_MSIX_VECTORS OCTEP_MAX_OQ
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/* Flags to disable and enable Interrupts */
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#define OCTEP_INPUT_INTR (1)
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#define OCTEP_OUTPUT_INTR (2)
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#define OCTEP_MBOX_INTR (4)
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#define OCTEP_ALL_INTR 0xff
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#define OCTEP_IQ_INTR_RESEND_BIT 59
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#define OCTEP_OQ_INTR_RESEND_BIT 59
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#define OCTEP_MMIO_REGIONS 3
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/* PCI address space mapping information.
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* Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of
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* Octeon gets mapped to different physical address spaces in
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* the kernel.
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*/
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struct octep_mmio {
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/* The physical address to which the PCI address space is mapped. */
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u8 __iomem *hw_addr;
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/* Flag indicating the mapping was successful. */
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int mapped;
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};
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struct octep_pci_win_regs {
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u8 __iomem *pci_win_wr_addr;
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u8 __iomem *pci_win_rd_addr;
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u8 __iomem *pci_win_wr_data;
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u8 __iomem *pci_win_rd_data;
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};
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struct octep_hw_ops {
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void (*setup_iq_regs)(struct octep_device *oct, int q);
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void (*setup_oq_regs)(struct octep_device *oct, int q);
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void (*setup_mbox_regs)(struct octep_device *oct, int mbox);
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irqreturn_t (*non_ioq_intr_handler)(void *ioq_vector);
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irqreturn_t (*ioq_intr_handler)(void *ioq_vector);
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int (*soft_reset)(struct octep_device *oct);
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void (*reinit_regs)(struct octep_device *oct);
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u32 (*update_iq_read_idx)(struct octep_iq *iq);
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void (*enable_interrupts)(struct octep_device *oct);
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void (*disable_interrupts)(struct octep_device *oct);
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void (*enable_io_queues)(struct octep_device *oct);
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void (*disable_io_queues)(struct octep_device *oct);
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void (*enable_iq)(struct octep_device *oct, int q);
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void (*disable_iq)(struct octep_device *oct, int q);
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void (*enable_oq)(struct octep_device *oct, int q);
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void (*disable_oq)(struct octep_device *oct, int q);
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void (*reset_io_queues)(struct octep_device *oct);
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void (*dump_registers)(struct octep_device *oct);
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};
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/* Octeon mailbox data */
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struct octep_mbox_data {
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u32 cmd;
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u32 total_len;
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u32 recv_len;
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u32 rsvd;
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u64 *data;
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};
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/* Octeon device mailbox */
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struct octep_mbox {
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/* A spinlock to protect access to this q_mbox. */
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spinlock_t lock;
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u32 q_no;
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u32 state;
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/* SLI_MAC_PF_MBOX_INT for PF, SLI_PKT_MBOX_INT for VF. */
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u8 __iomem *mbox_int_reg;
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/* SLI_PKT_PF_VF_MBOX_SIG(0) for PF,
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* SLI_PKT_PF_VF_MBOX_SIG(1) for VF.
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*/
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u8 __iomem *mbox_write_reg;
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/* SLI_PKT_PF_VF_MBOX_SIG(1) for PF,
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* SLI_PKT_PF_VF_MBOX_SIG(0) for VF.
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*/
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u8 __iomem *mbox_read_reg;
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struct octep_mbox_data mbox_data;
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};
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/* Tx/Rx queue vector per interrupt. */
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struct octep_ioq_vector {
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char name[OCTEP_MSIX_NAME_SIZE];
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struct napi_struct napi;
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struct octep_device *octep_dev;
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struct octep_iq *iq;
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struct octep_oq *oq;
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cpumask_t affinity_mask;
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};
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/* Octeon hardware/firmware offload capability flags. */
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#define OCTEP_CAP_TX_CHECKSUM BIT(0)
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#define OCTEP_CAP_RX_CHECKSUM BIT(1)
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#define OCTEP_CAP_TSO BIT(2)
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/* Link modes */
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enum octep_link_mode_bit_indices {
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OCTEP_LINK_MODE_10GBASE_T = 0,
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OCTEP_LINK_MODE_10GBASE_R,
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OCTEP_LINK_MODE_10GBASE_CR,
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OCTEP_LINK_MODE_10GBASE_KR,
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OCTEP_LINK_MODE_10GBASE_LR,
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OCTEP_LINK_MODE_10GBASE_SR,
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OCTEP_LINK_MODE_25GBASE_CR,
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OCTEP_LINK_MODE_25GBASE_KR,
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OCTEP_LINK_MODE_25GBASE_SR,
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OCTEP_LINK_MODE_40GBASE_CR4,
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OCTEP_LINK_MODE_40GBASE_KR4,
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OCTEP_LINK_MODE_40GBASE_LR4,
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OCTEP_LINK_MODE_40GBASE_SR4,
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OCTEP_LINK_MODE_50GBASE_CR2,
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OCTEP_LINK_MODE_50GBASE_KR2,
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OCTEP_LINK_MODE_50GBASE_SR2,
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OCTEP_LINK_MODE_50GBASE_CR,
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OCTEP_LINK_MODE_50GBASE_KR,
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OCTEP_LINK_MODE_50GBASE_LR,
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OCTEP_LINK_MODE_50GBASE_SR,
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OCTEP_LINK_MODE_100GBASE_CR4,
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OCTEP_LINK_MODE_100GBASE_KR4,
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OCTEP_LINK_MODE_100GBASE_LR4,
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OCTEP_LINK_MODE_100GBASE_SR4,
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OCTEP_LINK_MODE_NBITS
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};
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/* Hardware interface link state information. */
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struct octep_iface_link_info {
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/* Bitmap of Supported link speeds/modes. */
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u64 supported_modes;
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/* Bitmap of Advertised link speeds/modes. */
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u64 advertised_modes;
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/* Negotiated link speed in Mbps. */
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u32 speed;
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/* MTU */
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u16 mtu;
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/* Autonegotation state. */
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#define OCTEP_LINK_MODE_AUTONEG_SUPPORTED BIT(0)
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#define OCTEP_LINK_MODE_AUTONEG_ADVERTISED BIT(1)
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u8 autoneg;
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/* Pause frames setting. */
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#define OCTEP_LINK_MODE_PAUSE_SUPPORTED BIT(0)
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#define OCTEP_LINK_MODE_PAUSE_ADVERTISED BIT(1)
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u8 pause;
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/* Admin state of the link (ifconfig <iface> up/down */
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u8 admin_up;
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/* Operational state of the link: physical link is up down */
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u8 oper_up;
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};
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/* The Octeon device specific private data structure.
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* Each Octeon device has this structure to represent all its components.
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*/
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struct octep_device {
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struct octep_config *conf;
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/* Octeon Chip type. */
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u16 chip_id;
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u16 rev_id;
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/* Device capabilities enabled */
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u64 caps_enabled;
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/* Device capabilities supported */
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u64 caps_supported;
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/* Pointer to basic Linux device */
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struct device *dev;
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/* Linux PCI device pointer */
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struct pci_dev *pdev;
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/* Netdev corresponding to the Octeon device */
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struct net_device *netdev;
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/* memory mapped io range */
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struct octep_mmio mmio[OCTEP_MMIO_REGIONS];
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/* MAC address */
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u8 mac_addr[ETH_ALEN];
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/* Tx queues (IQ: Instruction Queue) */
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u16 num_iqs;
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/* pkind value to be used in every Tx hardware descriptor */
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u8 pkind;
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/* Pointers to Octeon Tx queues */
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struct octep_iq *iq[OCTEP_MAX_IQ];
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/* Rx queues (OQ: Output Queue) */
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u16 num_oqs;
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/* Pointers to Octeon Rx queues */
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struct octep_oq *oq[OCTEP_MAX_OQ];
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/* Hardware port number of the PCIe interface */
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u16 pcie_port;
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/* PCI Window registers to access some hardware CSRs */
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struct octep_pci_win_regs pci_win_regs;
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/* Hardware operations */
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struct octep_hw_ops hw_ops;
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/* IRQ info */
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u16 num_irqs;
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u16 num_non_ioq_irqs;
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char *non_ioq_irq_names;
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struct msix_entry *msix_entries;
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/* IOq information of it's corresponding MSI-X interrupt. */
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struct octep_ioq_vector *ioq_vector[OCTEP_MAX_QUEUES];
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/* Hardware Interface Tx statistics */
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struct octep_iface_tx_stats iface_tx_stats;
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/* Hardware Interface Rx statistics */
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struct octep_iface_rx_stats iface_rx_stats;
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/* Hardware Interface Link info like supported modes, aneg support */
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struct octep_iface_link_info link_info;
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/* Mailbox to talk to VFs */
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struct octep_mbox *mbox[OCTEP_MAX_VF];
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/* Work entry to handle Tx timeout */
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struct work_struct tx_timeout_task;
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/* control mbox over pf */
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struct octep_ctrl_mbox ctrl_mbox;
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/* offset for iface stats */
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u32 ctrl_mbox_ifstats_offset;
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/* Work entry to handle ctrl mbox interrupt */
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struct work_struct ctrl_mbox_task;
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};
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static inline u16 OCTEP_MAJOR_REV(struct octep_device *oct)
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{
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u16 rev = (oct->rev_id & 0xC) >> 2;
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return (rev == 0) ? 1 : rev;
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}
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static inline u16 OCTEP_MINOR_REV(struct octep_device *oct)
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{
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return (oct->rev_id & 0x3);
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}
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/* Octeon CSR read/write access APIs */
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#define octep_write_csr(octep_dev, reg_off, value) \
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writel(value, (octep_dev)->mmio[0].hw_addr + (reg_off))
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#define octep_write_csr64(octep_dev, reg_off, val64) \
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writeq(val64, (octep_dev)->mmio[0].hw_addr + (reg_off))
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#define octep_read_csr(octep_dev, reg_off) \
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readl((octep_dev)->mmio[0].hw_addr + (reg_off))
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#define octep_read_csr64(octep_dev, reg_off) \
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readq((octep_dev)->mmio[0].hw_addr + (reg_off))
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/* Read windowed register.
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* @param oct - pointer to the Octeon device.
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* @param addr - Address of the register to read.
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*
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* This routine is called to read from the indirectly accessed
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* Octeon registers that are visible through a PCI BAR0 mapped window
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* register.
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* @return - 64 bit value read from the register.
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*/
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static inline u64
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OCTEP_PCI_WIN_READ(struct octep_device *oct, u64 addr)
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{
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u64 val64;
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addr |= 1ull << 53; /* read 8 bytes */
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writeq(addr, oct->pci_win_regs.pci_win_rd_addr);
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val64 = readq(oct->pci_win_regs.pci_win_rd_data);
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dev_dbg(&oct->pdev->dev,
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"%s: reg: 0x%016llx val: 0x%016llx\n", __func__, addr, val64);
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return val64;
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}
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/* Write windowed register.
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* @param oct - pointer to the Octeon device.
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* @param addr - Address of the register to write
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* @param val - Value to write
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*
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* This routine is called to write to the indirectly accessed
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* Octeon registers that are visible through a PCI BAR0 mapped window
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* register.
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* @return Nothing.
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*/
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static inline void
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OCTEP_PCI_WIN_WRITE(struct octep_device *oct, u64 addr, u64 val)
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{
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writeq(addr, oct->pci_win_regs.pci_win_wr_addr);
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writeq(val, oct->pci_win_regs.pci_win_wr_data);
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dev_dbg(&oct->pdev->dev,
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"%s: reg: 0x%016llx val: 0x%016llx\n", __func__, addr, val);
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}
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extern struct workqueue_struct *octep_wq;
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int octep_device_setup(struct octep_device *oct);
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int octep_setup_iqs(struct octep_device *oct);
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void octep_free_iqs(struct octep_device *oct);
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void octep_clean_iqs(struct octep_device *oct);
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int octep_setup_oqs(struct octep_device *oct);
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void octep_free_oqs(struct octep_device *oct);
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void octep_oq_dbell_init(struct octep_device *oct);
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void octep_device_setup_cn93_pf(struct octep_device *oct);
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int octep_iq_process_completions(struct octep_iq *iq, u16 budget);
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int octep_oq_process_rx(struct octep_oq *oq, int budget);
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void octep_set_ethtool_ops(struct net_device *netdev);
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#endif /* _OCTEP_MAIN_H_ */
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